/************************************************************************* $Archive: /PACS/OnBoard/m_smcsco.c $ $Revision: 1.10 $ $Date: 2009/04/23 13:51:12 $ $Author: amazy $ $Log: m_smcsco.c,v $ Revision 1.10 2009/04/23 13:51:12 amazy 6.029 * * 8 5/14/04 6:32p Pacs Egse * * 7 5/05/04 4:34p Pacs Egse * * 6 28/08/02 11:49 Amazy * Added the header with the history log *************************************************************************/ /***************************************************************************** * * Project name: Herschel PACS DEC-MEC * Product name: DM_LLDRV * Object name: m_smcsco * Filename: %M% * Language: C (ADSP-21020) * Compiler: G21K - r3.3 * Company: CRISA * Author: F. Torrero * Version: %I% * Creation date: 25/Mar/2002 * Last Modification date: %G% * * Description =============================================================== * * This module implements the configuration functions for two SMCS chips * * Change log =============================================================== * * | DATE | NEW VERSION | AUTHOR | REASON FOR CHANGE | * =========================================================================== * * 25/Mar/02 1 F.Torrero Creation * * ****************************************************************************/ /***************************************************************************** INCLUDES *****************************************************************************/ #include "l_gendef.h" #include "l_errcod.h" #include "m_smcsge.h" #include "m_smcsco.h" /***************************************************************************** PRIVATE CONSTANTS *****************************************************************************/ /* Nominal configuration values for SMCS registers */ #define K_SMCS1_SICR_CONF_VALUE 0x02 // SMCS1 is working in Little Endian (interface with DPU and SPU) #define K_SMCS1_TRS_CTRL_CONF_VALUE 0x10 #define K_SMCS1_IMR_CONF_VALUE 0x00 #define K_SMCS1_RT_CTRL_CONF_VALUE 0x00 #define K_SMCS1_COMI_CS0R_CONF_VALUE 0x20 #define K_SMCS2_SICR_CONF_VALUE 0x06 // SMCS2 is working in Big Endian (interface with DECs and BOLC) #define K_SMCS2_TRS_CTRL_CONF_VALUE 0x10 #define K_SMCS2_IMR_CONF_VALUE 0x00 #define K_SMCS2_RT_CTRL_CONF_VALUE 0x00 #define K_SMCS2_COMI_CS0R_CONF_VALUE 0x20 #define K_CH1_DSM_MODR_CONF_VALUE 0x0C #define K_CH2_DSM_MODR_CONF_VALUE 0x0C #define K_CH3_DSM_MODR_CONF_VALUE 0x0C #define K_CH1_COMICFG_CONF_VALUE 0x33 #define K_CH2_COMICFG_CONF_VALUE 0x33 #define K_CH3_COMICFG_CONF_VALUE 0x33 #define K_CH1_CNTRL1_CONF_VALUE 0x00 #define K_CH2_CNTRL1_CONF_VALUE 0x00 #define K_CH3_CNTRL1_CONF_VALUE 0x00 #define K_CH4_DSM_MODR_CONF_VALUE 0x0C #define K_CH5_DSM_MODR_CONF_VALUE 0x0C #define K_CH6_DSM_MODR_CONF_VALUE 0x0C #define K_CH4_COMICFG_CONF_VALUE 0x33 #define K_CH5_COMICFG_CONF_VALUE 0x33 #define K_CH6_COMICFG_CONF_VALUE 0x33 #define K_CH4_CNTRL1_CONF_VALUE 0x00 #define K_CH5_CNTRL1_CONF_VALUE 0x00 #define K_CH6_CNTRL1_CONF_VALUE 0x00 /***************************************************************************** PRIVATE TYPES *****************************************************************************/ /***************************************************************************** PRIVATE VARIABLES *****************************************************************************/ /***************************************************************************** DECLARATION OF PRIVATE FUNCTIONS *****************************************************************************/ /***************************************************************************** IMPLEMENTATION OF FUNCTIONS *****************************************************************************/ /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_ConfigureSMCSNominal * * DESCRIPTION * Configure specified SMCS chip to nominal values * * INPUT ARGUMENTS: * SMCSChip * * OUTPUT ARGUMENTS: * None * * RETURNED VALUE: * Status return * * PSEUDOCODE * If SMCSChip = Chip1 then * Write nominal configuration value into Chip1 SICR * Write nominal configuration value into Chip1 TRS_CTRL * Read Chip1 ISR and perform workaround i.e, dummy writing to 7F * Write nominal configuration value into Chip1 IMR * Write nominal configuration value into Chip1 RT_CTRL * Write nominal configuration value into Chip1 COMI_CS0R * Write nominal configuration value into Chip1 CHx_DSM_MODR (channels 1, 2 and 3) * Write nominal configuration value into Chip1 CHx_COMICFG (channels 1, 2 and 3) * Write nominal configuration value into Chip1 CHx_CTRL1 (channels 1, 2 and 3) * else (SMCSChip = Chip2) * Write nominal configuration value into Chip2 SICR * Write nominal configuration value into Chip2 TRS_CTRL * Read Chip2 ISR and perform workaround i.e, dummy writing to 7F * Write nominal configuration value into Chip2 IMR * Write nominal configuration value into Chip2 RT_CTRL * Write nominal configuration value into Chip2 COMI_CS0R * Write nominal configuration value into Chip2 CHx_DSM_MODR (channels 4, 5 and 6) * Write nominal configuration value into Chip2 CHx_COMICFG (channels 4, 5 and 6) * Write nominal configuration value into Chip2 CHx_CTRL1 (channels 4, 5 and 6) * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_ConfigureSMCSNominal(T_UNSIGNED_32 SMCSChip) { T_UNSIGNED_32 ISRValue=0; /* Just used to perform the reading */ if (SMCSChip == K_SMCS_1) { DSMCS_WriteSMCSReg(K_DMADD_SMCS1_SICR,K_SMCS1_SICR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_TRS_CTRL,K_SMCS1_TRS_CTRL_CONF_VALUE); DSMCS_ReadSMCSReg(K_DMADD_SMCS1_ISR,&ISRValue); /* Read and clear */ DSMCS_WriteSMCSReg(K_DMADD_SMCS1_DUMMY,0); /* Workaround (dummy writing) */ DSMCS_WriteSMCSReg(K_DMADD_SMCS1_IMR,K_SMCS1_IMR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_RT_CTRL,K_SMCS1_RT_CTRL_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_COMI_CS0R,K_SMCS1_COMI_CS0R_CONF_VALUE); // DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH1_DSM_MODR,K_CH1_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH1_DSM_MODR,0); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH2_DSM_MODR,K_CH2_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH3_DSM_MODR,K_CH3_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH1_COMICFG,K_CH1_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH2_COMICFG,K_CH2_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH3_COMICFG,K_CH3_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH1_CNTRL1,K_CH1_CNTRL1_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH2_CNTRL1,K_CH2_CNTRL1_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS1_CH3_CNTRL1,K_CH3_CNTRL1_CONF_VALUE); } else { /* SMCSChip is chip 2 */ DSMCS_WriteSMCSReg(K_DMADD_SMCS2_SICR,K_SMCS2_SICR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_TRS_CTRL,K_SMCS2_TRS_CTRL_CONF_VALUE); DSMCS_ReadSMCSReg(K_DMADD_SMCS2_ISR,&ISRValue); /* Read and clear */ DSMCS_WriteSMCSReg(K_DMADD_SMCS2_DUMMY,0); /* Workaround (dummy writing) */ DSMCS_WriteSMCSReg(K_DMADD_SMCS2_IMR,K_SMCS2_IMR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_RT_CTRL,K_SMCS2_RT_CTRL_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_COMI_CS0R,K_SMCS2_COMI_CS0R_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH4_DSM_MODR,K_CH4_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH5_DSM_MODR,K_CH5_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH6_DSM_MODR,K_CH6_DSM_MODR_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH4_COMICFG,K_CH4_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH5_COMICFG,K_CH5_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH6_COMICFG,K_CH6_COMICFG_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH4_CNTRL1,K_CH4_CNTRL1_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH5_CNTRL1,K_CH5_CNTRL1_CONF_VALUE); DSMCS_WriteSMCSReg(K_DMADD_SMCS2_CH6_CNTRL1,K_CH6_CNTRL1_CONF_VALUE); } return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_SetChannelTxSpeed * * DESCRIPTION * Set transmission speed value on specified channel * * INPUT ARGUMENTS: * Channel * Transmission speed * * OUTPUT ARGUMENTS: * None * * RETURNED VALUE: * Status return * * PSEUDOCODE * StatusReturn = OK * If Channel is 1 or 2 or 3 then * read SMCS1/TRS_CTRL * if TRS_CTRL != SMCS1/TRS_CTRL conf value then * StatusReturn = error (TRS_CTRL has not the nominal value) * else (channel is 4, 5 or 6) * read SMCS2/TRS_CTRL * if TRS_CTRL != SMCS2/TRS_CTRL conf value then * StatusReturn = error (TRS_CTRL has not the nominal value) * If StatusReturn is OK then * Determine address for specified channel of CHx_DSM_MODR * Step from current speed to final speed, doing one step at a time, by * reading CHx_DSM_MODR, masking old speed bits and ORing with new * speed bits. * Return StatusReturn *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_SetChannelTxSpeed(T_UNSIGNED_32 Channel, T_UNSIGNED_32 TxSpeed) { T_SR StatusReturn=K_SR_OK; T_UNSIGNED_32 TRS_CTRLValue=0; T_UNSIGNED_32 CHx_DSM_MODRRegisterAddress=0; T_UNSIGNED_32 CHx_DSM_MODRRegisterValue=0; T_UNSIGNED_32 CurrentTxSpeed=0; if ((Channel==K_SMCSCHANNEL_1)||(Channel==K_SMCSCHANNEL_2) ||(Channel==K_SMCSCHANNEL_3)) { DSMCS_ReadSMCSReg(K_DMADD_SMCS1_TRS_CTRL,&TRS_CTRLValue); if(TRS_CTRLValue != K_SMCS1_TRS_CTRL_CONF_VALUE) { StatusReturn =K_SR_ERROR_SMCS_TRS_CTRL_NOTNOM; } } else { /* Channel is 4, 5 or 6 */ DSMCS_ReadSMCSReg(K_DMADD_SMCS2_TRS_CTRL,&TRS_CTRLValue); if(TRS_CTRLValue != K_SMCS2_TRS_CTRL_CONF_VALUE) { StatusReturn =K_SR_ERROR_SMCS_TRS_CTRL_NOTNOM; } } if (StatusReturn == K_SR_OK) { /* Determine register address depending on selected channel */ CHx_DSM_MODRRegisterAddress=DSMCS_GetRegAddressForChannel(Channel, K_DMADD_SMCS1_CH1_DSM_MODR); /* Determine current speed */ DSMCS_GetChannelTxSpeed(Channel,&CurrentTxSpeed); /* Step from current to final speed */ while(CurrentTxSpeed!=TxSpeed) { if(CurrentTxSpeed>TxSpeed) { CurrentTxSpeed--; } else { CurrentTxSpeed++; } DSMCS_ReadSMCSReg(CHx_DSM_MODRRegisterAddress,&CHx_DSM_MODRRegisterValue); /* Mask old speed bits */ CHx_DSM_MODRRegisterValue=CHx_DSM_MODRRegisterValue & (~K_BMASK_CHx_DSM_MODR_TXSPEED); CHx_DSM_MODRRegisterValue=CHx_DSM_MODRRegisterValue | CurrentTxSpeed; DSMCS_WriteSMCSReg(CHx_DSM_MODRRegisterAddress,CHx_DSM_MODRRegisterValue); } } return(StatusReturn); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_GetChannelTxSpeed * * DESCRIPTION * Get transmission speed value for specified channel * * INPUT ARGUMENTS: * Channel * * OUTPUT ARGUMENTS: * Transmission speed * * RETURNED VALUE: * Status return * * PSEUDOCODE * StatusReturn = OK * If Channel is 1 or 2 or 3 then * read SMCS1/TRS_CTRL * if TRS_CTRL != SMCS1/TRS_CTRL conf value then * StatusReturn = error (TRS_CTRL has not the nominal value) * else (channel is 4, 5 or 6) * read SMCS2/TRS_CTRL * if TRS_CTRL != SMCS2/TRS_CTRL conf value then * StatusReturn = error (TRS_CTRL has not the nominal value) * If StatusReturn is OK then * Determine address for specified channel of CHx_DSM_MODR * TxSpeed=CHx_DSM_MODR reg. value with all but the Tx Speed bites masked * Return StatusReturn *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_GetChannelTxSpeed(T_UNSIGNED_32 Channel, T_UNSIGNED_32 *TxSpeed) { T_SR StatusReturn=K_SR_OK; T_UNSIGNED_32 TRS_CTRLValue=0; T_UNSIGNED_32 CHx_DSM_MODRRegisterAddress=0; T_UNSIGNED_32 CHx_DSM_MODRRegisterValue=0; if ((Channel==K_SMCSCHANNEL_1)||(Channel==K_SMCSCHANNEL_2) ||(Channel==K_SMCSCHANNEL_3)) { DSMCS_ReadSMCSReg(K_DMADD_SMCS1_TRS_CTRL,&TRS_CTRLValue); if(TRS_CTRLValue != K_SMCS1_TRS_CTRL_CONF_VALUE) { StatusReturn =K_SR_ERROR_SMCS_TRS_CTRL_NOTNOM; } } else { /* Channel is 4, 5 or 6 */ DSMCS_ReadSMCSReg(K_DMADD_SMCS2_TRS_CTRL,&TRS_CTRLValue); if(TRS_CTRLValue != K_SMCS2_TRS_CTRL_CONF_VALUE) { StatusReturn =K_SR_ERROR_SMCS_TRS_CTRL_NOTNOM; } } if (StatusReturn == K_SR_OK) { /* Determine register address depending on selected channel */ CHx_DSM_MODRRegisterAddress=DSMCS_GetRegAddressForChannel(Channel, K_DMADD_SMCS1_CH1_DSM_MODR); DSMCS_ReadSMCSReg(CHx_DSM_MODRRegisterAddress,&CHx_DSM_MODRRegisterValue); (*TxSpeed)=CHx_DSM_MODRRegisterValue & K_BMASK_CHx_DSM_MODR_TXSPEED; } return(StatusReturn); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_SetChannelTxPortWidth * * DESCRIPTION * Set transmission port width on specified channel * * INPUT ARGUMENTS: * Channel * Width * * OUTPUT ARGUMENTS: * None * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_COMICFG * Read CHx_COMICFG, mask old Tx port width bits and OR with new bits. * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_SetChannelTxPortWidth(T_UNSIGNED_32 Channel, T_UNSIGNED_32 Width) { T_UNSIGNED_32 CHx_COMICFGRegisterAddress=0; T_UNSIGNED_32 CHx_COMICFGRegisterValue=0; /* Determine register address depending on selected channel */ CHx_COMICFGRegisterAddress= DSMCS_GetRegAddressForChannel(Channel,K_DMADD_SMCS1_CH1_COMICFG); DSMCS_ReadSMCSReg(CHx_COMICFGRegisterAddress,&CHx_COMICFGRegisterValue); /* Mask old Tx port width bits */ CHx_COMICFGRegisterValue=CHx_COMICFGRegisterValue & (~K_BMASK_CHx_COMICFG_TXPORTWIDTH); CHx_COMICFGRegisterValue=CHx_COMICFGRegisterValue | Width; DSMCS_WriteSMCSReg(CHx_COMICFGRegisterAddress,CHx_COMICFGRegisterValue); return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_GetChannelTxPortWidth * * DESCRIPTION * Get transmission port width for specified channel * * INPUT ARGUMENTS: * Channel * * OUTPUT ARGUMENTS: * Width * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_COMICFG * Width = CHx_COMICFG reg. value with all but the Tx port width bites masked * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_GetChannelTxPortWidth(T_UNSIGNED_32 Channel, T_UNSIGNED_32 *Width) { T_UNSIGNED_32 CHx_COMICFGRegisterAddress=0; T_UNSIGNED_32 CHx_COMICFGRegisterValue=0; /* Determine register address depending on selected channel */ CHx_COMICFGRegisterAddress=DSMCS_GetRegAddressForChannel(Channel, K_DMADD_SMCS1_CH1_COMICFG); DSMCS_ReadSMCSReg(CHx_COMICFGRegisterAddress,&CHx_COMICFGRegisterValue); (*Width)=CHx_COMICFGRegisterValue & K_BMASK_CHx_COMICFG_TXPORTWIDTH; return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_SetChannelRxPortWidth * * DESCRIPTION * Set reception port width on specified channel * * INPUT ARGUMENTS: * Channel * Width * * OUTPUT ARGUMENTS: * None * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_COMICFG * Read CHx_COMICFG, mask old Rx port width bits and OR * with (new bits left-shifted to correct position). * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_SetChannelRxPortWidth(T_UNSIGNED_32 Channel, T_UNSIGNED_32 Width) { T_UNSIGNED_32 CHx_COMICFGRegisterAddress=0; T_UNSIGNED_32 CHx_COMICFGRegisterValue=0; /* Determine register address depending on selected channel */ CHx_COMICFGRegisterAddress=DSMCS_GetRegAddressForChannel(Channel, K_DMADD_SMCS1_CH1_COMICFG); DSMCS_ReadSMCSReg(CHx_COMICFGRegisterAddress,&CHx_COMICFGRegisterValue); /* Mask old Rx port width bits */ CHx_COMICFGRegisterValue=CHx_COMICFGRegisterValue & (~K_BMASK_CHx_COMICFG_RXPORTWIDTH); CHx_COMICFGRegisterValue=CHx_COMICFGRegisterValue | (Width << K_BPOS_CHx_COMICFG_RXPORTWIDTH); DSMCS_WriteSMCSReg(CHx_COMICFGRegisterAddress,CHx_COMICFGRegisterValue); return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_GetChannelRxPortWidth * * DESCRIPTION * Get reception port width for specified channel * * INPUT ARGUMENTS: * Channel * * OUTPUT ARGUMENTS: * Width * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_COMICFG * Width = (CHx_COMICFG reg. value with all but the Tx port * width bites masked) right-shifted to position "0" * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_GetChannelRxPortWidth(T_UNSIGNED_32 Channel, T_UNSIGNED_32 *Width) { T_UNSIGNED_32 CHx_COMICFGRegisterAddress=0; T_UNSIGNED_32 CHx_COMICFGRegisterValue=0; /* Determine register address depending on selected channel */ CHx_COMICFGRegisterAddress=DSMCS_GetRegAddressForChannel(Channel, K_DMADD_SMCS1_CH1_COMICFG); DSMCS_ReadSMCSReg(CHx_COMICFGRegisterAddress,&CHx_COMICFGRegisterValue); (*Width)=(CHx_COMICFGRegisterValue & K_BMASK_CHx_COMICFG_RXPORTWIDTH) >> K_BPOS_CHx_COMICFG_RXPORTWIDTH; return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_EnaDisSMCSChecksum * * DESCRIPTION * Enable/Disable the checksum generation and checking for the specified channel * * INPUT ARGUMENTS: * Channel * Enable/disable flag * * OUTPUT ARGUMENTS: * None * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_CNTRL1 * Read CHx_CNTRL1, * If flag = Enable then set checksum enable bit * Else reset checksum enable bit * Write new CHx_CNTRL1 reg. value * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_EnaDisSMCSChecksum(T_UNSIGNED_32 Channel, T_UNSIGNED_32 EnableDisableFlag) { T_UNSIGNED_32 CHx_CNTRL1RegisterAddress=0; /* Determine register address depending on selected channel */ CHx_CNTRL1RegisterAddress= DSMCS_GetRegAddressForChannel(Channel,K_DMADD_SMCS1_CH1_CNTRL1); if (EnableDisableFlag==K_ENABLE) { DSMCS_WriteBitInSMCSReg(CHx_CNTRL1RegisterAddress, K_BPOS_CHx_CNTRL1_CHECKSUMENA,K_HIGH); } else { /* disable */ DSMCS_WriteBitInSMCSReg(CHx_CNTRL1RegisterAddress, K_BPOS_CHx_CNTRL1_CHECKSUMENA,K_LOW); } return(K_SR_OK); } /* #$# ----------------------------------------------------------------------- * FUNCTION NAME: DSMCS_GetSMCSChecksumStatus * * DESCRIPTION * Get checksum generation and checking status for the specified channel * * INPUT ARGUMENTS: * Channel * * OUTPUT ARGUMENTS: * Enable/disable status * * RETURNED VALUE: * Status return * * PSEUDOCODE * Determine address for specified channel of CHx_CNTRL1 * Read ChecksumEnable bit in CHx_CNTRL1 reg. (using memory module * functions) * If Checksumbit=1 then Enable/disable Status = Enable * Else Enable/disable Status=disable * Return OK *---------------------------------------------------------------------- $#$ */ T_SR DSMCS_GetSMCSChecksumStatus(T_UNSIGNED_32 Channel, T_UNSIGNED_32 *EnableDisableStatus) { T_UNSIGNED_32 CHx_CNTRL1RegisterAddress=0; T_BOOLEAN IsChecksumEnabled=K_FALSE; /* Determine register address depending on selected channel */ CHx_CNTRL1RegisterAddress= DSMCS_GetRegAddressForChannel(Channel,K_DMADD_SMCS1_CH1_CNTRL1); IsChecksumEnabled=DSMCS_CheckBitInSMCSReg(CHx_CNTRL1RegisterAddress, K_BPOS_CHx_CNTRL1_CHECKSUMENA); if (IsChecksumEnabled==K_TRUE) { (*EnableDisableStatus)=K_ENABLE; } else { (*EnableDisableStatus)=K_DISABLE; } return(K_SR_OK); }