/************************************************************************* $Archive: /PACS/OnBoard/l_hwmap.h $ $Revision: 1.10 $ $Date: 2009/04/23 13:51:12 $ $Author: amazy $ $Log: l_hwmap.h,v $ Revision 1.10 2009/04/23 13:51:12 amazy 6.029 * * 4 28/08/02 11:49 Amazy * Added the header with the history log *************************************************************************/ /***************************************************************************** * * Project name: Plank LFI REBA / Herschel PACS SPU * Product name: LLSW_DRV * Object name: l_hwmap * Filename: %M% * Language: C (ADSP-21020) * Compiler: G21K - r3.3 * Company: CRISA * Author: F. Torrero * Version: %I% * Creation date: 14/Sep/2001 * Last Modification date: %G% * * Description =============================================================== * * This module defines constants related to hardware mappping, memory and * PSCs * * Change log =============================================================== * * | DATE | NEW VERSION | AUTHOR | REASON FOR CHANGE | * =========================================================================== * * 14/Sep/01 1 F.Torrero Creation * * ****************************************************************************/ #ifndef L_HWMAP_H #define L_HWMAP_H /***************************************************************************** INCLUDES *****************************************************************************/ /***************************************************************************** PROVIDED CONSTANTS *****************************************************************************/ /* Hardware unit (subsystem) identifier. These IDs are the values defined in SRD, where the 3 MSB bits of the ID byte are used to identify the subsystem. Note that since there is no difference between PACS/SPU/SWL and LWL for LLSW_DRW or SPU_SUSW purposes, both are identified with the same code (which corresponds to LWL) */ #define K_HWUNITID_REBA_DPU 0x00 #define K_HWUNITID_REBA_SPU 0x80 #define K_HWUNITID_PACS_SPU 0x60 /* Program memory and data memory identifiers These IDs are the values defined in SRD, where the bit 4 (being 0 the LSB) of the ID byte is used to identify the Program/Data memory.*/ #define K_MEMID_PROGRAM_MEMORY 0x00 #define K_MEMID_DATA_MEMORY 0x10 /* Memory area identifiers These IDs are the values defined in SRD, where the 4 LSB of the ID byte are used to identify the memory area. These constants do not take into account if it is Program or data memory. */ #define K_MEMID_PROM 0x0 #define K_MEMID_RAM 0x1 #define K_MEMID_EXTRAM 0x2 #define K_MEMID_EEPROM 0x3 #define K_MEMID_SMCSDPRAM 0x4 #define K_MEMID_1553DPRAM 0x5 /* Memory area identifiers for specific Program/Data memory areas These constants do take into account if it is Program or data memory, being the ID a combination of the Program/Data ID and the Area ID. */ #define K_MEMAREAID_PROGRAM_RAM K_MEMID_PROGRAM_MEMORY + K_MEMID_RAM #define K_MEMAREAID_EEPROM K_MEMID_PROGRAM_MEMORY + K_MEMID_EEPROM #define K_MEMAREAID_PROM K_MEMID_PROGRAM_MEMORY + K_MEMID_PROM #define K_MEMAREAID_DATA_RAM K_MEMID_DATA_MEMORY + K_MEMID_RAM #define K_MEMAREAID_EXT_DATA_RAM K_MEMID_DATA_MEMORY + K_MEMID_EXTRAM /* PROGRAM MEMORY MAP ---------------------------------------------------- */ /* Program Memory base addresses at APSW execution */ #define K_PMADDR_BASE_PRAM 0x000000 /* Program RAM */ #define K_PMADDR_BASE_EEPROM 0x0E0000 /* EEPROM, REBA/DPU and PACS/SPU only!! */ #define K_PMADDR_BASE_MIRR_ROM 0x180000 /* Mirrored ROM */ #define K_PMADDR_BASE_PMPSC 0xFFFF00 /* PMPSC register set */ /* Program Memory base addresses at Start-up SW execution */ #define K_PMADDR_ATSU_BASE_PROM 0x000000 /* Program ROM */ #define K_PMADDR_ATSU_BASE_PRAM 0x800000 /* Area 0 of Program RAM */ #define K_PMADDR_ATSU_BASE_EEPROM 0x8E0000 /* EEPROM, REBA/DPU and PACS/SPU only!! */ /* Program memory sizes (number of 48bit words) */ #define K_PMSIZE_PRAM 0x080000 /* Program RAM */ #define K_PMSIZE_EEPROM 0x040000 /* EEPROM, REBA/DPU and PACS/SPU only!! */ #define K_PMSIZE_PROM 0x008000 /* PROM and Mirrored PROM */ /* Last addresses for Program RAM and EEPROM at APSW execution */ #define K_PMADDR_LAST_PRAM K_PMADDR_BASE_PRAM+K_PMSIZE_PRAM-1 #define K_PMADDR_LAST_EEPROM K_PMADDR_BASE_EEPROM+K_PMSIZE_EEPROM-1 /* Last addresses for Program RAM, EEPROM and PROM at Start-up SW execution */ #define K_PMADDR_ATSU_LAST_PRAM K_PMADDR_ATSU_BASE_PRAM+K_PMSIZE_PRAM-1 #define K_PMADDR_ATSU_LAST_EEPROM K_PMADDR_ATSU_BASE_EEPROM+K_PMSIZE_EEPROM-1 #define K_PMADDR_ATSU_LAST_PROM K_PMADDR_ATSU_BASE_PROM+K_PMSIZE_PROM-1 /* -------------------------------------------------------------------------*/ /* DATA MEMORY MAP ---------------------------------------------------- */ /* Data memory base addresses */ #define K_DMADDR_BASE_DRAM 0x00000000 /* Data RAM */ #define K_DMADDR_BASE_SMCS 0x20020000 /* SMCS Register set */ #define K_DMADDR_BASE_DAU 0x20040000 /* DAU Register set, REBA/DPU only!! */ #define K_DMADDR_BASE_1553DPRAM 0x40080000 /* 1553 Dual Port RAM, REBA/DPU only!! */ #define K_DMADDR_BASE_1553 0x40100000 /* 1553 Register set, REBA/DPU only!! */ #define K_DMADDR_BASE_EXTDRAM 0x80000000 /* Extended DRAM, REBA/SPU & PACS/SPU only!!*/ #define K_DMADDR_BASE_SMCSDPRAM 0x40100000 /* SMCS Dual Port RAM */ #define K_DMADDR_BASE_DMPSC 0xFFFFFF00 /* DMPSC register set */ /* Data memory sizes (number of 32bit words, except in 1553DPRAM which is 16bit wide) */ #define K_DMSIZE_DRAM 0x00080000 #define K_DMSIZE_1553DPRAM 0x00002000 /* 1553 Dual Port RAM, REBA/DPU only!! */ #define K_DMSIZE_EXTDRAM 0x00080000 /* Extended DRAM, REBA/SPU & PACS/SPU only!!*/ #define K_DMSIZE_SMCSDPRAM 0x00002000 /* SMCS Dual Port RAM */ /* Last addresses for Data RAM and Extended Data RAM at APSW execution */ #define K_DMADDR_LAST_DRAM K_DMADDR_BASE_DRAM+K_DMSIZE_DRAM-1 #define K_DMADDR_LAST_EXTDRAM K_DMADDR_BASE_EXTDRAM+K_DMSIZE_EXTDRAM-1 #ifdef MOSAIC_BOARD /* DEC-MEC data memory map constants - only applicable to DEC-MEC! */ /* DEC-MEC additional memory base addresses */ #define K_DMADDR_BASE_SMCS1 0x00022000 /* SMCS 1 Register set, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS2 0x00022100 /* SMCS 2 Register set, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS1DPRAM 0x00020000 /* SMCS 1 Dual Port RAM, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS2DPRAM 0x00021000 /* SMCS 2 Dual Port RAM, DEC-MEC only! */ /* DEC-MEC additional memory sizes */ #define K_DMSIZE_SMCS1DPRAM 0x00001000 /* SMCS 1 Dual Port RAM, DEC-MEC only! */ #define K_DMSIZE_SMCS2DPRAM 0x00001000 /* SMCS 2 Dual Port RAM, DEC-MEC only! */ #else // if CRISA_BOARD /* DEC-MEC data memory map constants - only applicable to DEC-MEC! */ /* DEC-MEC additional memory base addresses */ #define K_DMADDR_BASE_SMCS1 0x20020000 /* SMCS 1 Register set, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS2 0x40080000 /* SMCS 2 Register set, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS1DPRAM 0x40380000 /* SMCS 1 Dual Port RAM, DEC-MEC only! */ #define K_DMADDR_BASE_SMCS2DPRAM 0x40100000 /* SMCS 2 Dual Port RAM, DEC-MEC only! */ /* DEC-MEC additional memory sizes */ #define K_DMSIZE_SMCS1DPRAM 0x00002000 /* SMCS 1 Dual Port RAM, DEC-MEC only! */ #define K_DMSIZE_SMCS2DPRAM 0x00002000 /* SMCS 2 Dual Port RAM, DEC-MEC only! */ /* -------------------------------------------------------------------------*/ #endif // MOSAIC_BOARD /* Interrupt bit positions within DSP21020/irptl and imask registers */ #define K_BPOS_DSPINT_SOVFI 3 /* Bit 3: Add: 18: Stack overflow */ #define K_BPOS_DSPINT_TMZHI 4 /* Bit 4: Add: 20: Timer = 0 (high priority) */ #define K_BPOS_DSPINT_IRQ3I 5 /* Bit 5: Add: 28: IRQ3- asserted */ #define K_BPOS_DSPINT_IRQ2I 6 /* Bit 6: Add: 30: IRQ2- asserted */ #define K_BPOS_DSPINT_IRQ1I 7 /* Bit 7: Add: 38: IRQ1- asserted */ #define K_BPOS_DSPINT_IRQ0I 8 /* Bit 8: Add: 40: IRQ0- asserted */ #define K_BPOS_DSPINT_CB7I 11 /* Bit 11: Add: 58: Circ. buffer 7 overflow */ #define K_BPOS_DSPINT_CB15I 12 /* Bit 12: Add: 60: Circ. buffer 15 overflow */ #define K_BPOS_DSPINT_TMZLI 14 /* Bit 14: Add: 70: Timer = 0 (low priority) */ #define K_BPOS_DSPINT_FIXI 15 /* Bit 15: Add: 78: Fixed-pt. overflow */ #define K_BPOS_DSPINT_FLTOI 16 /* Bit 16: Add: 80: fltg-pt. overflow */ #define K_BPOS_DSPINT_FLTUI 17 /* Bit 17: Add: 88: fltg-pt. underflow */ #define K_BPOS_DSPINT_FLTII 18 /* Bit 18: Add: 90: fltg-pt. invalid */ #define K_BPOS_DSPINT_SFT0I 24 /* Bit 24: Add: C0: user software int 0 */ #define K_BPOS_DSPINT_SFT1I 25 /* Bit 25: Add: C8: user software int 1 */ #define K_BPOS_DSPINT_SFT2I 26 /* Bit 26: Add: D0: user software int 2 */ #define K_BPOS_DSPINT_SFT3I 27 /* Bit 27: Add: D8: user software int 3 */ #define K_BPOS_DSPINT_SFT4I 28 /* Bit 28: Add: E0: user software int 4 */ #define K_BPOS_DSPINT_SFT5I 29 /* Bit 29: Add: E8: user software int 5 */ #define K_BPOS_DSPINT_SFT6I 30 /* Bit 30: Add: F0: user software int 6 */ #define K_BPOS_DSPINT_SFT7I 31 /* Bit 31: Add: F8: user software int 7 */ #define K_BPOS_DSPINT_MILSTD1553 K_BPOS_DSPINT_IRQ3I /* REBA/DPU only!! */ #define K_BPOS_DSPINT_SMCS K_BPOS_DSPINT_IRQ2I #define K_BPOS_DSPINT_DMPSC K_BPOS_DSPINT_IRQ1I #define K_BPOS_DSPINT_PMPSC K_BPOS_DSPINT_IRQ0I /* Interrupt bit masks for DSP21020/irptl and imask registers */ #define K_BMASK_DSPINT_SOVFI 0x8 #define K_BMASK_DSPINT_TMZHI 0x10 #define K_BMASK_DSPINT_IRQ3I 0x20 #define K_BMASK_DSPINT_IRQ2I 0x40 #define K_BMASK_DSPINT_IRQ1I 0x80 #define K_BMASK_DSPINT_IRQ0I 0x100 #define K_BMASK_DSPINT_CB7I 0x800 #define K_BMASK_DSPINT_CB15I 0x1000 #define K_BMASK_DSPINT_TMZLI 0x4000 #define K_BMASK_DSPINT_FIXI 0x8000 #define K_BMASK_DSPINT_FLTOI 0x10000 #define K_BMASK_DSPINT_FLTUI 0x20000 #define K_BMASK_DSPINT_FLTII 0x40000 #define K_BMASK_DSPINT_SFT0I 0x1000000 #define K_BMASK_DSPINT_SFT1I 0x2000000 #define K_BMASK_DSPINT_SFT2I 0x4000000 #define K_BMASK_DSPINT_SFT3I 0x8000000 #define K_BMASK_DSPINT_SFT4I 0x10000000 #define K_BMASK_DSPINT_SFT5I 0x20000000 #define K_BMASK_DSPINT_SFT6I 0x40000000 #define K_BMASK_DSPINT_SFT7I 0x80000000 #define K_BMASK_DSPINT_ALL 0xFF07D9F8 #define K_BMASK_DSPINT_MILSTD1553 K_BMASK_DSPINT_IRQ3I /* REBA/DPU only!! */ #define K_BMASK_DSPINT_SMCS K_BMASK_DSPINT_IRQ2I #define K_BMASK_DSPINT_DMPSC K_BMASK_DSPINT_IRQ1I #define K_BMASK_DSPINT_PMPSC K_BMASK_DSPINT_IRQ0I /* Program Memory PSC register addresses */ #define K_PMADD_PMPSC_GENCONFSTT K_PMADDR_BASE_PMPSC + 0x00 #define K_PMADD_PMPSC_CONFBANK0 K_PMADDR_BASE_PMPSC + 0x01 #define K_PMADD_PMPSC_CONFBANK1 K_PMADDR_BASE_PMPSC + 0x02 #define K_PMADD_PMPSC_CONFBANK2 K_PMADDR_BASE_PMPSC + 0x03 #define K_PMADD_PMPSC_CONFBANK3 K_PMADDR_BASE_PMPSC + 0x04 #define K_PMADD_PMPSC_INTP K_PMADDR_BASE_PMPSC + 0x05 #define K_PMADD_PMPSC_INTMASK K_PMADDR_BASE_PMPSC + 0x06 #define K_PMADD_PMPSC_INTRST K_PMADDR_BASE_PMPSC + 0x07 #define K_PMADD_PMPSC_INTVECTOR K_PMADDR_BASE_PMPSC + 0x08 #define K_PMADD_PMPSC_INTTEST K_PMADDR_BASE_PMPSC + 0x09 #define K_PMADD_PMPSC_SFADD K_PMADDR_BASE_PMPSC + 0x0A #define K_PMADD_PMPSC_DFADD K_PMADDR_BASE_PMPSC + 0x0B /* UART Registers not used, offset 0x0C to 0x11 */ #define K_PMADD_PMPSC_OBTCONF K_PMADDR_BASE_PMPSC + 0x12 #define K_PMADD_PMPSC_TIMERCYCLES K_PMADDR_BASE_PMPSC + 0x13 #define K_PMADD_PMPSC_OBTSCUPDT16 K_PMADDR_BASE_PMPSC + 0x14 #define K_PMADD_PMPSC_OBTUPDT32 K_PMADDR_BASE_PMPSC + 0x15 #define K_PMADD_PMPSC_EXTOBTREG K_PMADDR_BASE_PMPSC + 0x17 #define K_PMADD_PMPSC_INTOBTREG K_PMADDR_BASE_PMPSC + 0x18 #define K_PMADD_PMPSC_TCONF K_PMADDR_BASE_PMPSC + 0x19 #define K_PMADD_PMPSC_TINIVAL K_PMADDR_BASE_PMPSC + 0x1A #define K_PMADD_PMPSC_TINISCALER K_PMADDR_BASE_PMPSC + 0x1B #define K_PMADD_PMPSC_TIMERREG K_PMADDR_BASE_PMPSC + 0x1C #define K_PMADD_PMPSC_GPIOCONF K_PMADDR_BASE_PMPSC + 0x1D #define K_PMADD_PMPSC_GPIOREG K_PMADDR_BASE_PMPSC + 0x1E /* Data Memory PSC register addresses */ #define K_DMADD_DMPSC_GENCONFSTT K_DMADDR_BASE_DMPSC + 0x00 #define K_DMADD_DMPSC_CONFBANK0 K_DMADDR_BASE_DMPSC + 0x01 #define K_DMADD_DMPSC_CONFBANK1 K_DMADDR_BASE_DMPSC + 0x02 #define K_DMADD_DMPSC_CONFBANK2 K_DMADDR_BASE_DMPSC + 0x03 #define K_DMADD_DMPSC_CONFBANK3 K_DMADDR_BASE_DMPSC + 0x04 #define K_DMADD_DMPSC_INTP K_DMADDR_BASE_DMPSC + 0x05 #define K_DMADD_DMPSC_INTMASK K_DMADDR_BASE_DMPSC + 0x06 #define K_DMADD_DMPSC_INTRST K_DMADDR_BASE_DMPSC + 0x07 #define K_DMADD_DMPSC_INTVECTOR K_DMADDR_BASE_DMPSC + 0x08 #define K_DMADD_DMPSC_INTTEST K_DMADDR_BASE_DMPSC + 0x09 #define K_DMADD_DMPSC_SFADD K_DMADDR_BASE_DMPSC + 0x0A #define K_DMADD_DMPSC_DFADD K_DMADDR_BASE_DMPSC + 0x0B /* UART Registers not used, offset 0x0C to 0x11 */ #define K_DMADD_DMPSC_OBTCONF K_DMADDR_BASE_DMPSC + 0x12 #define K_DMADD_DMPSC_TIMERCYCLES K_DMADDR_BASE_DMPSC + 0x13 #define K_DMADD_DMPSC_OBTSCUPDT16 K_DMADDR_BASE_DMPSC + 0x14 #define K_DMADD_DMPSC_OBTUPDT32 K_DMADDR_BASE_DMPSC + 0x15 #define K_DMADD_DMPSC_EXTOBTREG K_DMADDR_BASE_DMPSC + 0x17 #define K_DMADD_DMPSC_INTOBTREG K_DMADDR_BASE_DMPSC + 0x18 #define K_DMADD_DMPSC_TCONF K_DMADDR_BASE_DMPSC + 0x19 #define K_DMADD_DMPSC_TINIVAL K_DMADDR_BASE_DMPSC + 0x1A #define K_DMADD_DMPSC_TINISCALER K_DMADDR_BASE_DMPSC + 0x1B #define K_DMADD_DMPSC_TIMERREG K_DMADDR_BASE_DMPSC + 0x1C #define K_DMADD_DMPSC_GPIOCONF K_DMADDR_BASE_DMPSC + 0x1D #define K_DMADD_DMPSC_GPIOREG K_DMADDR_BASE_DMPSC + 0x1E /* Positions of bits within GENCONFSTT register */ #define K_BPOS_GENCONFSTT_WDT 15 /* State of input signal WDOBT */ #define K_BPOS_GENCONFSTT_WDRST 14 /* Reset is Watchdog */ #define K_BPOS_GENCONFSTT_DFRST 13 /* Reset is DEF */ #define K_BPOS_GENCONFSTT_PURST 12 /* Reset is power up */ #define K_BPOS_GENCONFSTT_ENINT 11 /* Enable global interrupts */ #define K_BPOS_GENCONFSTT_INTRSTDF 8 /* Generate Reset on DEF */ /* Bit masks for PSC/GENCONFSTT register */ #define K_BMASK_CONFBANKx_BxIO0ENEDAC 0x00000002 /* Positions of bits within CONFBANKx registers */ #define K_BPOS_CONFBANKx_BxIO2DISCHECK 16 #define K_BPOS_CONFBANKx_BxIO1DISCHECK 9 #define K_BPOS_CONFBANKx_BxIO0DISCHECK 2 /* Positions of bits within TCONF register */ #define K_BPOS_TCONF_TMODE 1 #define K_BPOS_TCONF_ENT 0 /* Positions of bits within OBTCONF register */ #define K_BPOS_OBTCONF_PRCOUNTERS 8 #define K_BPOS_OBTCONF_LOCKTIMER 3 #define K_BPOS_OBTCONF_ENWD 0 /* Bit positions within PSC/INTP, INTMASK, INTRST registers */ #define K_BPOS_PSCINT_SF 14 /* EDAC SEF interrupt */ #define K_BPOS_PSCINT_INTT 12 /* PSC Timer interrupt */ #define K_BPOS_PSCINT_INTEXT2 5 /* External interrupt 2 */ #define K_BPOS_PSCINT_INTEXT1 4 /* External interrupt 1 */ #define K_BPOS_PSCINT_INTEXT0 3 /* External interrupt 0 */ #define K_BPOS_PSCINT_INTBT 2 /* Bus Timeout Interrupt */ #define K_BPOS_PSCINT_INTOBTWD 1 /* OBT/WD Counter Interrupt */ #define K_BPOS_PSCINT_DF 0 /* EDAC DEF Interrupt */ #define K_BPOS_DMPSCINT_DAEDATARDY K_BPOS_PSCINT_INTEXT2 /* DAE Data Ready, in DMPSC REBA/DPU Only!!*/ #define K_BPOS_PSCINT_DAUEOA K_BPOS_PSCINT_INTEXT1 /* DAU End of Adquisition, in PMPSC of REBA/DPU Only!!*/ #define K_BPOS_PSCINT_1HZ K_BPOS_PSCINT_INTEXT0 /* 1Hz Interrupt, in PMPSC REBA/DPU Only!!*/ /* Bit masks for PSC/INTP, INTMASK, INTRST registers */ #define K_BMASK_PSCINT_SF 0x4000 #define K_BMASK_PSCINT_INTT 0x1000 #define K_BMASK_PSCINT_INTEXT2 0x20 #define K_BMASK_PSCINT_INTEXT1 0x10 #define K_BMASK_PSCINT_INTEXT0 0x8 #define K_BMASK_PSCINT_INTBT 0x4 #define K_BMASK_PSCINT_INTOBTWD 0x2 #define K_BMASK_PSCINT_DF 0x1 #define K_BMASK_PSCINT_ALL 0x7fff #define K_BMASK_DMPSCINT_DAEDATARDY K_BMASK_PSCINT_INTEXT2 #define K_BMASK_PSCINT_DAUEOA K_BMASK_PSCINT_INTEXT1 #define K_BMASK_PSCINT_1HZ K_BMASK_PSCINT_INTEXT0 #define K_BMASK_PSCINT_SF_AND_DF K_BMASK_PSCINT_SF + K_BMASK_PSCINT_DF /* GPIO outputs (all in DMPSC), bit positions for registers GPIOCONF and GPIOREG */ #define K_GPOUTPUT_EEPROMWREN 14 #define K_GPOUTPUT_EN2LVDSIF 13 #define K_GPOUTPUT_EN1LVDSIF 12 #define K_GPOUTPUT_SPURESET 9 #define K_GPOUTPUT_SMCSRESET 8 #define K_GPOUTPUT_SETHIGH1HZ 7 #define K_GPOUTPUT_SETLOW1HZ 6 #define K_GPOUTPUT_DAESMCSRES2N 5 #define K_GPOUTPUT_DAESMCSRES1N 4 /* DEC-MEC additional GPIO outputs - only applicable to DEC-MEC! */ #define K_GPOUTPUT_EN2LVDSIFSMCS1 13 #define K_GPOUTPUT_EN1LVDSIFSMCS1 12 #define K_GPOUTPUT_SMCS2RESET 11 #define K_GPOUTPUT_ENLVDSIFSMCS2 10 #define K_GPOUTPUT_SMCS1RESET 8 /* GPIO inputs (all in DMPSC), bit positions for registers GPIOCONF and GPIOREG */ #define K_GPINPUT_EEPROM_RDY_BUSY 15 #define K_GPINPUT_DAEPWRSTS 1 #define K_GPINPUT_OBTCLOCKSTS 0 #endif /* L_HWMAP_H */