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  PUBLICATION_DATE = 2006-09-26
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END
                           TABLE 8
                     DPU characteristics

Item             Specification
Central          Rad-hard Temic processor based on Analog
microprocessor   Devices ADSP21020, 20 MHz,
                60 MFLOPS, data transfer from local memory
                to mass memory 38 Mbit s-1
Mass memory      4 Gbit net
Program memory   8 kbyte (8 bit) PROM (bootstrap kernel)
                256 kword (48 bit) E2PROM (OS, task-specific
                program modules)
                256 kword (48 bit) program SRAM
                All program memory latch-up and SEU immune
Local data       4 Mword (32 bit) fast SRAM for local image
memory           storage
                128 kbyte non-volatile E2PROM
                128 kword (32 bit) fast SRAM for
                stack/variables storage
                (zero wait state, latch-up and SEU immune)
Digital          Serial command I/F to NAC CRB and WAC CRB
interfaces       Serial data I/F to NAC CRB and WAC CRB
                Serial command and data I/F to MCB
                Serial command and data I/F to PCM
                Spacecraft I/F
                IEEE 1355 interface to S/C SSMM
Redundancy       Processing Element, S/C-interface: dual cold
                redundant
                MMB: graceful degradation
Protection       SEL: latch-up detectors (MMB only)
against          SEU: memory error correction, SSCDSD (MMB
single event     only)
errors           DSP watchdog
Power management Nominal and low power mode, implemented by:
                a) program SRAM deselect,
                b) clock disable of DIB A or DIB B, c) MMB
                switch-off
Operating system Real-time operating system (Virtuoso)