14-06-04 (AM + ER + BM) ======================= in case of grounding problem: 3278 check that temp sensors are ok: hk diag with 571 - 572 (23b - 23c) Values are wrong (1680565016). Check MUXADDR on the backplane. All seems good but J2-C12 (on MIM1): no signal. Replaced FPGA by 3_1(3) (the one with MASTER RESET too short). Signal on J2-C12 is correct Temp sensors are still not working. hk diag with 433 - 434 (1b1 - 1b2) (reprogrammed CUSTOM_HK_1-2 to look at ChopperTemperatureSensorVoltage and Grating) The values do not really changes. Looked at MIM2, the enable of the last 2 MUX is always at 1. We should replace the component that have already been replaced twice (74AC138). Replaced FPGA by the latest one (3_1(4)). We still have the wrong MUXADDR so, the problem comes from the FPGA (not a dust or the socket). Test the Master Reset. The 1355 link is lost aftet the reset. Added 2 commands to restart the links 100msec after the master reset. Changed the time-out after a master reset : if (KS_SemaTestWT(SEMA_BLUE_DEC_SECOND_TO_LAST_READOUT_RECEIVED, 64) == RC_TIME) the time out is now 2000 to take into account the slow readout frequency after reset (64Hz instead of 256Hz). Tested the Heater commands. They failed. The code was obsolete. Corrected. Tested the chopper. It is unstable with the parameters that were stable at CSL. Benoit sets new parameters: Kp = 0x493e0; Ki = 0x1312d00; Kd = 0x258; Kf = 0x804; Tested the grating. While homing, It bounced. Retried many times. No more problem. 15-06-04 (AM + ER + BM + FM + EC) ================================= Found a copy/paste problem in the DEC hk. Vdda is copied twice in the hk. The second one must be replaced by VddaCurrent Desoldered the 74HCT540 on MIM2 (not replaced yet). Rework on MIM1, a suspect wire could short-circuit 2.5V and 15V (J2-B6). Desoldered the 74AC138 on MIM2. Resoldered the 74AC540 and 74AC138 on MIM2. Added 1K resistors on the 3 address lines between the FPGA and the 74AC138 on MIM2 Started the acceptance test procedure. 16-06-04 (AM + FM + EC) ======================= Disconnected the overshoot killer on the DATA board. Continued the acceptance test. Started the OBS audit. 17-06-04 (AM + FM + EC) ======================= Continued the OBS audit. Changed the potentiometer setting to recalibrate the range of the ADC of the DATA board (ref is VSS). Continued the acceptance test. During the latest functionnal test, the FW did not stop on position. The hk analog is incorrect. It seems that some values are not at the right place (i.e : the 5V ref voltage has the behaviour of a temperature sensor voltage). Made a temporary version of the OBS to monitor the hk index. It appears the the bit3 of the index (bit19 of the register) stays at 0. We checked on the backplane if it was on the data bus. It seems ok. Put the timing FPGA we had for delivery. The hk index is incrementing fine. We found a short-circuit on MIM1 between MIMWR and GND. Removed it. And back to the latest FPGA (3_1(4)). Tested the FW: OK, grating: OK, chopper: OK, temp sensors: OK. For acceptance test problem, see Helmut's list. 20:30 Let's have a beer and eat some saussages. 18-06-04 (AM + FM + EC) ======================= Moved next to cryostat with the DMC + PC EGSE + our FPU. Tried homing the grating, it bounced many times (during 44-1-1). Looked with Hk diag. It seems that within 1ms, the error gets bigger than 3°. Could not find yet the reason. Started to test the switch-on procedure with HF. The second connection with DPU (after SPU switch on) fails 50% of the time. 19-06-04 (AM + EC + BM) ======================= Once we switched on BOLC, we lost the connection between DPU-DMC. Found that the smcs 1 was configured to autoreconnect. Removed it and it solved the DPU-DMC connection problems. Tried to switch on the DECs, after a few seconds, the DECs reach FIFO_FULL (no connection loss). Tried again with smcs 2 configured to autoreconnect. No change. Back to the first lab. Looked at the bad transmission of commands to DEC. When we send 0x40, the DEC receives 0x80. We suspect that bit 6 & 7 are swapped somewhere between Bus - DPRAM - SMCS. Ask CRISA for details. Looked at the Grating problem, the excitation sinus is not regular. It comes from the 8KHz that has jitter. With OBT connected, if the soft is running or not, it does not change anything : jitter of 2µs max. Without OBT, no jitter when the soft is not running but up to 10µs jitter when the soft is running. Checked the OBT, the signal is not clean (some transition are doubled, this can explain the 2µs jitter). Reduced the OBS, removed the access to FPGA -> still have the jitter (less often). Commented out the content of the ISR -> no more jitter. Made a stupid software with no access to Memory -> no more jitter. Upgraded the stupid software to access memory (with LSb of address the same as FPGA LSB address) -> no more jitter. 20-06-04 (AM + EC + BM) ======================= OBT probs : see Anomaly report (by EC). Tried the grating now that the excitation signal is correct. No progress (small oscillation). The grating is loose, tighten the screws. Even worse: big oscillation. 21-06-04 (AM + FM + BM + ER) ============================ Replaced a chip 90C32 by 26C32 on MIM1. The OBT is cleaner now. The DMC does not count 131072 but 131380. The OBT is still not perfect, some glitches are still seen so this could explain the frequency difference (but the difference seems to be very constant...). The cable between the OBT box and the DMC is 1000Kohms. Without this cable, we have now a perfect counting of the OBT!!! Performed a test suggested by CRISA to detect defaults on the CRISA boards. When accessing the SMCS ISR register, we see that the bits are swapped two. Returned the results to CRISA. CRISA suggested to take pictures of the boards. Done While inspecting the CRISA board, we found unsolded capacitors near the LVDS of smcs 2 . Corrected. 22-06-04 (AM + FM + BM + ER) ============================ Showed the working OBT to MPE. Martin will provide a new cable. Moved to the Cryostat Lab. Connected to our PC EGSE. Started to test the connection between CPU and DECs. The connection lasted for 3-4 hours (even while doing measures on the DECs). Repeated the acceptance test (DEC section). All voltages are measured with voltmeter and checked in the HK. GR1, 2 and 3 are perfect (both analog measurement and hk), on GR 4, analog measures are perfect. The hk shows some discrepency with other groups. Note that on group 4, the 0V reference is different from the other group and, it appears that it uses bit6-7 (that are swapped). We re-computed the values by hand. This explains partially the discrepencies. All this should be checked again when the CRISA board is corrected. Tested Bias commanding: (with the CRISA board bug !!) Set of parameters sent: dec hex 32 20 8 8 8000 0V 0 1V FFF 20 8 8000 1V FFF 1V FFF CRE integration : --------------- Checked grounding continuity between the table, the cryostat, the connectors: OK Martin connects harness on cryostat side. Francis connects harness on DMC side. Test setup: ---------- DMC connected to CRE in the cryostat. DMC commanded by DPU-SIM Science data sent to LinkReceiver (dummy SPU) on a second EGSE PC. The LinkReceiver is configured to receive packets and store them on disk (with circular file numbering). For the first test of CRE, in order to be able to see all datas on the EGSE, we will keep the slow readout frequency on DEC. Here is the set of parameters used: dec hex ClockPerReadout 128 80 ReadoutPerRamp 8 8 CreCtrlReg 8000 BiasR 0V 0 ZeroBias 0V 0 test procedure to test the Red CRE: ---------------------------------- 2-19-0 to switch red DEC ON checked HK, OK same as without CRE connected 2-21-0 to switch red detector array 2-12-0 to switch blue DEC ON 2-14-0 to switch blue detector array here is the HK we have (smallest capacitor is selected and CRE are inactive ) (Voltages in Volts and currents in µA) : DMC_DECR_VDDD_1 DMC_DECR_VSS_1 DMC_DECR_VGND_1 DMC_DECR_VCAN1_1 DMC_DECR_VCAN2_1 DMC_DECR_V0BIAS_1 DMC_DECR_VBI_R_1 DMC_DECR_V0V_1 DMC_DECR_VSCP_1 DMC_DECR_VDDR_1 DMC_DECR_VDDA_1 DMC_DECR_VWELL_1 DMC_DECR_IDDA_1 DMC_DECR_IDDD_1 DMC_DECR_ISS_1 DMC_DECR_ISUB_1 2.500686666 -2.999053926 -0.000152593 0.539414655 1.899929807 -0.000457778 -0.000762963 0 -0.099185156 -0.399029511 2.499771111 3.001037629 -4.943998535 -0.068666646 -248.0468154 -0.015259255 DMC_DECR_VDDD_2 DMC_DECR_VSS_2 DMC_DECR_VGND_2 DMC_DECR_VCAN1_2 DMC_DECR_VCAN2_2 DMC_DECR_V0BIAS_2 DMC_DECR_VBI_R_2 DMC_DECR_V0V_2 DMC_DECR_VSCP_2 DMC_DECR_VDDR_2 DMC_DECR_VDDA_2 DMC_DECR_VWELL_2 DMC_DECR_IDDA_2 DMC_DECR_IDDD_2 DMC_DECR_ISS_2 DMC_DECR_ISUB_2 2.501449629 -3.000122074 0.000305185 0.498519852 1.931516465 0 0.000152593 0.000305185 -0.088198492 -0.399334696 2.500991852 3.001495407 250.0076296 -0.015259255 -250 0.007629627 DMC_DECB_VDDD_3 DMC_DECB_VSS_3 DMC_DECB_VGND_3 DMC_DECB_VCAN1_3 DMC_DECB_VCAN2_3 DMC_DECB_V0BIAS_3 DMC_DECB_VBI_R_3 DMC_DECB_V0V_3 DMC_DECB_VSCP_3 DMC_DECB_VDDR_3 DMC_DECB_VDDA_3 DMC_DECB_VWELL_3 DMC_DECB_IDDA_3 DMC_DECB_IDDD_3 DMC_DECB_ISS_3 DMC_DECB_ISUB_3 2.697073275 -3.001190222 -0.000305185 0.501419111 1.902066103 -0.00061037 -0.000762963 -0.000152593 -0.100405896 -0.400555437 2.501297037 3.001800592 250.0076296 -0.007629627 -250 -0.007629627 DMC_DECB_VDDD_4 DMC_DECB_VSS_4 DMC_DECB_VGND_4 DMC_DECB_VCAN1_4 DMC_DECB_VCAN2_4 DMC_DECB_V0BIAS_4 DMC_DECB_VBI_R_4 DMC_DECB_V0V_4 DMC_DECB_VSCP_4 DMC_DECB_VDDR_4 DMC_DECB_VDDA_4 DMC_DECB_VWELL_4 DMC_DECB_IDDA_4 DMC_DECB_IDDD_4 DMC_DECB_ISS_4 DMC_DECB_ISUB_4 2.487868892 -3.007599109 -0.026245918 0.493331706 1.881008332 -0.025940733 -0.026093326 -0.025940733 -0.115054781 -0.404675436 2.4877163 4.262825404 250.0076296 -1.30466628 -250 -1.30466628 Start LinkReceiver on EGSE PC (menu 3, 100 files) 2-86-1-1 to start link with red SPU 6-50-24-1-0 to forward science data to red SPU No ramps are seen. It is logical since the CRE active bit has not been set. 6-50-27-3-80-8-804D blue (temp sensors enabled, select biggest capacitor, and keep CRE ON) 2-16-0 set blue param 6-50-27-3-80-8-804F blue (CRE active) 2-16-0 set blue param 6-50-26-3-80-8-804D red (temp sensors enabled, select biggest capacitor, and keep CRE ON) 2-23-0 set red param 6-50-26-3-80-8-804F red (CRE active) 2-23-0 set red param here is the HK we have now: DMC_DECR_VDDD_1 DMC_DECR_VSS_1 DMC_DECR_VGND_1 DMC_DECR_VCAN1_1 DMC_DECR_VCAN2_1 DMC_DECR_V0BIAS_1 DMC_DECR_VBI_R_1 DMC_DECR_V0V_1 DMC_DECR_VSCP_1 DMC_DECR_VDDR_1 DMC_DECR_VDDA_1 DMC_DECR_VWELL_1 DMC_DECR_IDDA_1 DMC_DECR_IDDD_1 DMC_DECR_ISS_1 DMC_DECR_ISUB_1 2.499771111 -3.000122074 -0.000457778 0.505081332 1.89947203 -0.010681478 0.029602954 0 -0.099032563 -0.399945067 2.499771111 3.001037629 58.6260567 4.318369091 -70.46723838 0.083925901 DMC_DECR_VDDD_2 DMC_DECR_VSS_2 DMC_DECR_VGND_2 DMC_DECR_VCAN1_2 DMC_DECR_VCAN2_2 DMC_DECR_V0BIAS_2 DMC_DECR_VBI_R_2 DMC_DECR_V0V_2 DMC_DECR_VSCP_2 DMC_DECR_VDDR_2 DMC_DECR_VDDA_2 DMC_DECR_VWELL_2 DMC_DECR_IDDA_2 DMC_DECR_IDDD_2 DMC_DECR_ISS_2 DMC_DECR_ISUB_2 2.501144444 -3.000732444 -0.000152593 0.488143559 1.891994995 -0.025940733 0.030213324 0.000305185 -0.08865627 -0.399792474 2.501297037 3.001190222 250.0076296 3.624073 -250 0.091555528 DMC_DECB_VDDD_3 DMC_DECB_VSS_3 DMC_DECB_VGND_3 DMC_DECB_VCAN1_3 DMC_DECB_VCAN2_3 DMC_DECB_V0BIAS_3 DMC_DECB_VBI_R_3 DMC_DECB_V0V_3 DMC_DECB_VSCP_3 DMC_DECB_VDDR_3 DMC_DECB_VDDA_3 DMC_DECB_VWELL_3 DMC_DECB_IDDA_3 DMC_DECB_IDDD_3 DMC_DECB_ISS_3 DMC_DECB_ISUB_3 2.501602222 -3.003936888 -0.000915555 0.500656148 1.901150548 -0.016632588 0.029602954 -0.000152593 -0.099948119 -0.4013184 2.502365184 3.001648 68.47590564 4.966887417 -81.65990173 0.114444411 DMC_DECB_VDDD_4 DMC_DECB_VSS_4 DMC_DECB_VGND_4 DMC_DECB_VCAN1_4 DMC_DECB_VCAN2_4 DMC_DECB_V0BIAS_4 DMC_DECB_VBI_R_4 DMC_DECB_V0V_4 DMC_DECB_VSCP_4 DMC_DECB_VDDR_4 DMC_DECB_VDDA_4 DMC_DECB_VWELL_4 DMC_DECB_IDDA_4 DMC_DECB_IDDD_4 DMC_DECB_ISS_4 DMC_DECB_ISUB_4 2.487868892 -3.009125034 -0.026551103 0.49775689 1.880397961 -0.03173925 0.023499252 -0.025788141 -0.114597003 -0.405133213 2.48832667 2.973876156 250.0076296 3.158665731 -249.7558519 -1.251258889 deselect the CREs 6-50-27-3-80-8-804D blue (temp sensors enabled, select biggest capacitor, and keep CRE ON) 2-16-0 set blue param 6-50-26-3-80-8-804D red (temp sensors enabled, select biggest capacitor, and keep CRE ON) 2-23-0 set red param here is the HK we have now: DMC_DECR_VDDD_1 DMC_DECR_VSS_1 DMC_DECR_VGND_1 DMC_DECR_VCAN1_1 DMC_DECR_VCAN2_1 DMC_DECR_V0BIAS_1 DMC_DECR_VBI_R_1 DMC_DECR_V0V_1 DMC_DECR_VSCP_1 DMC_DECR_VDDR_1 DMC_DECR_VDDA_1 DMC_DECR_VWELL_1 DMC_DECR_IDDA_1 DMC_DECR_IDDD_1 DMC_DECR_ISS_1 DMC_DECR_ISUB_1 2.506179998 -2.998748741 0 0.506302072 1.899777215 -0.009765923 -0.016632588 0 -0.099185156 -0.399334696 2.499771111 3.001037629 53.91857662 -0.030518509 -62.50190741 -0.030518509 DMC_DECR_VDDD_2 DMC_DECR_VSS_2 DMC_DECR_VGND_2 DMC_DECR_VCAN1_2 DMC_DECR_VCAN2_2 DMC_DECR_V0BIAS_2 DMC_DECR_VBI_R_2 DMC_DECR_V0V_2 DMC_DECR_VSCP_2 DMC_DECR_VDDR_2 DMC_DECR_VDDA_2 DMC_DECR_VWELL_2 DMC_DECR_IDDA_2 DMC_DECR_IDDD_2 DMC_DECR_ISS_2 DMC_DECR_ISUB_2 2.501144444 -2.999969481 0.000152593 0.498214667 1.892605365 -0.025635548 -0.025788141 0.000305185 -0.08865627 -0.399487289 2.501144444 3.001037629 246.9328898 0.022888882 -250 0.022888882 DMC_DECR_VDDD_1 DMC_DECR_VSS_1 DMC_DECR_VGND_1 DMC_DECR_VCAN1_1 DMC_DECR_VCAN2_1 DMC_DECR_V0BIAS_1 DMC_DECR_VBI_R_1 DMC_DECR_V0V_1 DMC_DECR_VSCP_1 DMC_DECR_VDDR_1 DMC_DECR_VDDA_1 DMC_DECR_VWELL_1 DMC_DECR_IDDA_1 DMC_DECR_IDDD_1 DMC_DECR_ISS_1 DMC_DECR_ISUB_1 2.506179998 -2.998748741 0 0.506302072 1.899777215 -0.009765923 -0.016632588 0 -0.099185156 -0.399334696 2.499771111 3.001037629 53.91857662 -0.030518509 -62.50190741 -0.030518509 DMC_DECB_VDDD_4 DMC_DECB_VSS_4 DMC_DECB_VGND_4 DMC_DECB_VCAN1_4 DMC_DECB_VCAN2_4 DMC_DECB_V0BIAS_4 DMC_DECB_VBI_R_4 DMC_DECB_V0V_4 DMC_DECB_VSCP_4 DMC_DECB_VDDR_4 DMC_DECB_VDDA_4 DMC_DECB_VWELL_4 DMC_DECB_IDDA_4 DMC_DECB_IDDD_4 DMC_DECB_ISS_4 DMC_DECB_ISUB_4 2.487868892 -3.008209479 -0.026398511 0.493179113 1.880855739 -0.032197027 -0.032502213 -0.019837031 -0.109866634 -0.404828028 2.487868892 2.974028748 247.4669637 -1.037629322 -250 -1.319925535 select the CREs again 6-50-27-3-80-8-804F blue (CRE active) 2-16-0 set blue param 6-50-26-3-80-8-804F red (CRE active) 2-23-0 set red param change the BiasR to 50mV (C8) 6-50-27-4-80-8-804F-C8 blue (change BiasR to 50mV) 2-16-0 set blue param 6-50-26-4-80-8-804F-C8 red (change BiasR to 50mV) 2-23-0 set red param We don't see any ramps. look at the data (last pixel of the first line (dummy) of red group I) readout counter value 3 57897 2 58173 1 57937 0 57958 7 57978 The first line contains only FFFFFFFF. All missing modules contains FFFFFFF. Some pixels contain values around E32dE403 Some pixels contain values around 758975C2 Disconnected the harness. Performed the short functional test with our SPU : OK. 23-06-04 (AM + ER + BM) ======================= Performed the short functional test again with Helmut. Tested the temperature sensors: OK Check the OBT time stamping: OK (note we forgot to synchronize on BOLC before checking OBT counter in photo packets). removed the CRISA mezzanine and brang it to workshop for repair. Continue with CRISA main board only. Filter wheels test ------------------ Connected FW SPEC nominal used nominal commanding, everyting worked fine. made a complete turn in open loop. diag hk for FW spec: 22C 556 VMOTA 234 564 VMOTB 230 560 IMOTA 237 567 IMOTB 22B 555 POS_A 23F 559 POS_B see d:\prj\pacs\test Garching\FW_SPEC_1_TURN.xls 2 things we should understand: currents are measured zero voltages stay a long time at zero during movements. Connected FW PHOTO nominal used nominal commanding, can not see a position detected. made a complete turn in open loop. diag hk for FW phot: 22C 556 VMOTA 234 564 VMOTB 230 560 IMOTA 237 567 IMOTB 233 563 POS_A 239 569 POS_B The position sensors show a value near zero. The voltages are variable (looks good). But the hall sensors keep the same value Connected our filter wheel on the PHOTO connector. We could make it move. Connected the FPU PHOTO FW on the spectro connector on MIM3. It does not move. For information : filter wheel are driven in open loop by sine wave with an amplitude of 60 mA. connected the redundant spectro wheel : OK connected the redundant photo wheel : same as with nominal circuit compared the resistor values for both FW. more or less the same values Grating tests ------------- Benoit puts MIM1 and MIM3 on extension boards to make inductosyn tuning. First we connect to redundant grating. Inductosyn excitation signal is too small (between 100mV and 200mV instead of 2V). Checked the resistor value of the grating (44 ohms) + harness (16 ohms) : 60.0 ohms, OK Tried with the nominal grating, it is even worse: 67mV. We found that the resistor value on the sine/cosine line of the harness is 1350 ohms. (much more than on our harness). Tried to add 2*680 ohms resistor on each line of our harness. The sine/cosine has now decreased to 1V. Replaced the mezzanine board of the CRISA board. Replaced a DEC by a PC and sent 0x40 and 0x80. Bits are not swapped anymore. Choppper tests -------------- compiled a temporary version of the software where the chopper is commanded in open-loop. Connected the chopper, position when free looks ok but some small peaks (not influence by the primary pump the turbo pump is still running). Offset has been set to 2055 (should have been a different value see Zeiss report) Degree 0 -0.26mA -204 -CC -1 -4.3mA -3169 -C61 -2 -7.81mA -6142 -17FE -3 -11.58mA -9107 -2393 -4.1 -15.73mA -12370 -3052 -9 -35.06mA -27571 -6BB3 +1 +3.52mA 2768 AD0 +2 +7.31mA 5749 1675 +3 +11.14 8760 2238 +4.1 +15.31 12040 2F08 +9 +34.75 27328 6AC0 parameters used. Note we also changed some parameters in chopgrat.s directly (they would need to be adapted by command in the future). Kp = 0x927c0; Ki = 0x45cf180; Kd = 0x3c0; Kf = 0x8d0; Rate = 164; AccumulatorLimit = 0x7FFFFFFF; OutputLimit = 0x7fff; Scaling = 0; ErrorLimit = 0x7FFFFFFF; PosOffset = 2055; KiCurr = 0x64; CHOPPER WORKS FINE AT FIRST TRY !!!!! CRE tests (2) ------------- This time, we change the width of the non-dest sync to 2 CRE clock. Only the red array is connected. We can finally see some ramps. We tried with and without bias, with 1pF and 3pF. See "first ramps.xls" Grating tests (continued) ------------------------- Measure of the excitation current/voltages of inductosyn both on STM and on QM. All measures are identical. Removed 1/2 of the 8Kohms resistor. It doubles the signal. Removed the other 1/2 of the 8Kohms resistors and added one 100kohms. We have now 1V but 100bits of noise which is too much. Added 4 1nF capacitor on the entrance of sine/cosine. Still the same noise. 19-07-04 (AM + BM) ================== high CPU load ------------- Made some test while CPU load was high: SWOF_RDEC, CPU load goes from 75 to 62 SWOF_BDEC, CPU load goes from 62 to 24 Again when CPU load was high: SWOF_BDEC, CPU load goes from 75 to 36 SWOF_RDEC, CPU load goes from 36 to 24 So it seems that Blue DEC (or its link) is the source of our CPU load problem. As soon as DMC is in a situation where it has high CPU load, it is not more possible to send command to BOLC (everything looks fine in the hk but, obviously, it is not received by BOLC). The problem appears only after a long period of use of DMC. And disappears after a long switch-off (30 minutes). When it happens, the DEC FPGA bug happens almost at every packet. other 1355 problem ------------------ Other problem noticed, after a chip reset on DPU-DMC connection, the last command received by DMC is received again. Since it happens both with DPU SIM and real DPU (which are totally different related to chip reset strategy), it is most likely that the problem is on DMC side. Grating ------- We tried to unlock the grating (both closed-loop and open-loop commands) without success. We have not been able to configure the excitation signal properly due to insufficient range of potentiometer. A resistor must be added tomorrow by Francis. Chopper ------- Made a test in open-loop. The response is not exactly matching the model. Made some modification to the chopper algorithm (tested on the model). The chopper is stable and moves quite good but it does not seem optimal (we didn't check if it was in specs). Analog HK --------- At the end of the day, we noticed that the diag hk was not synchronized (i.e : values are acquired correctly but are not at the right place (we can see ramps in the REF_5V when the temperature sensors are on)). This seems to explain why we are not always able to drive the temperature sensors. 20-07-04 (AM + BM + FM) ======================= The analog hk is working fine this morning. So it seams that (like the CPU load problem), it is related to the temperature of DMC. So, we can read the temperature sensors: FW_SPEC = 1626 ohms FW_PHOT = 1573 CHOPPER = 1427 GRATING = 2759 FPU_T1 = 1682 FPU_T2 = 1551 CAL_SRC = 510 Introduced the chopper open-loop mode. It works fine. (2-57-1-100 to activate it, 2-57-1-0 to deactivate it) Burned OBS 5.007 in EEPROM. Now starting version 5.008. Introduced 11 new parameters to the chopper controller param block to be able to configure completely the controller without patching the OBS. Note, it also had some influence on the grating controller since they were using common code that could not be used anymore. Be carefull next time we use grating. Also added some more diagnostic hk to look at science data from DEC. Launch Lock ----------- FM+BM made some modification on MIM3 to be able to increase the current in the launch-lock. After that, in the hk, we still don't see the bits updated correctly (Launch-Locked bit is always at 1 while Launch_Unlocked is changing at any time). FM+BM looked at the voltages on the LL sensors, it appears that they are too close to the threshold (2.5). FM changes one resistor value to have this threshold at 5V. The bits in hk are now correct. We are able to move the LL many times in any direction. When using closed loop, The Launch lock does not go to the limit (it stops too early after the LL sensor has reached 5V Started to code the grating degraded mode (copied from FW controller). It is ready but not tested yet. Made a test from SCOS2000. After a while (30min), DMC is unstable again. There are 2 new entries in hk that we can monitor (the number of SMCS2 interrupt and the number of SMCS2 interrupt that are handled (the usefull one)). Here is what we see: NB Interrupts NB Interrupts handled 56069 1064 56053 1064 56054 1064 (2x512 for the DEC + 40 for the BOLC) Note: the total number of interrupts also take into account the interrupts from DMPSC but DMC_DM_SF_IND and DMC_DM_DF_IND are not incrementing so it seems that all interrupts are really coming from the SMCS chip. 27/7/2004 16:00 starting disassembly JMG + MvB