// $RCSfile: main.h,v $Revision: 1.4 $Date: 2005/03/11 15:08:57
#ifndef __MAIN_H__
#define __MAIN_H__

//---- Global defines  ----------------------------------------------------------------
// Addresses of hardware registers
#define LTXREGADD 	 (unsigned int*) 0x8c000000 		 /* LS R/W reg LowSpeed IF */
#define LRXREGADD 	 (unsigned int*) 0x8c000001 		 /* LS RX register Read */
#define LSTREGADD 	 (unsigned int*) 0x8c000002 		 /* LS status reg */
#define FRXREGADD_0	 (unsigned int*) 0x88000000 		 /* FIFO-0 RX register */
#define FRXREGADD_1	 (unsigned int*) 0x89000000 		 /* FIFO-1 RX register */
#define FRXREGADD_2	 (unsigned int*) 0x8a000000 		 /* FIFO-2 RX register */
#define FRXREGADD_3	 (unsigned int*) 0x8b000000 		 /* FIFO-3 RX register */
#define BRDREG_RST	 (unsigned int*) 0x8d000000 		 /* I/F Board reset register	(RW) */
#define BSTREGADD 	 (unsigned int*) 0x8d000001 		 /* Board Status Register */
#define IRQLEV 		 (unsigned int*) 0x83000000 		 /* IRQ Level Register */
#define IRQTYPE		 (unsigned int*) 0x83000001 		 /* IRQ LType Register */
#define IRQMASK		 (unsigned int*) 0x83000002 		 /* IRQ Mask Register */
#define IRQACK 		 (unsigned int*) 0x83000003 		 /* IRQ Acknowledge Register (W) */
#define EEPROM 		 (unsigned int*) 0x80000000 		 /* EEPROM addr */
#define HW_TIMER_CTRL 	(unsigned int*) 0x81000000 		 /* Special timer (in FPGA) for VM interrupt */
#define HW_TIMER_LOAD	(unsigned int*) (HW_TIMER_CTRL + 1)
#define HW_TIMER_READ	(unsigned int*) (HW_TIMER_CTRL + 2)
#define ICU_HK_SEL_REG	(unsigned int*) (ICU_HK_BASE_REG + MSEL_REG)  	/* ICU HK select register */
#define ICU_HK_DATA_REG (unsigned int*) (ICU_HK_BASE_REG + MDATA_REG)	/* ICU HK data register */

/* Registers for the ADC converter. MSEL_reg selects the line, MDATA_reg contains the 12bit output and one "ready" flag bit (the MSB) */
#define ICU_HK_BASE_REG 0x8F000000
#define MSEL_REG		0x8000
#define MDATA_REG 		0x8001

//---- Tasks ----------------------------------------------------------------
extern void entry_point (void);

#endif	// __MAIN_H__