/*================== RCS/CVS revision history hifisyntax.h: ===============
; This file is included also in the OBS SW
; 
==========================================================================*/
//; HIFI VM Code definition
//; ATTENTION: this file is also read as ifstream in the program
#ifndef HIFI_SYNTAX_H_
#define HIFI_SYNTAX_H_

//;---------+------+------+-------------+-----------------------------------
//;     Op  | Instr| # of | # of mem    |   Comment
//;     Code| Code | Param| locations   |
//;         |      |      | (address)   |
//;---------+------+------+-------------+-----------------------------------
#define CMD    7    // 2   1   ;Send_Command(addr, code, val)*  Send command code/val to SS addr
#define RCMD   0    // 2   1   ;Send_Command_Reg(addr, code, reg)*   Send command code/R[reg] to SS addr
#define MTX    1    // 1   1   ;Mutex(OnOff)    Lock/Unlock low speed I/F port
#define NOP    2    // 0   1   ;NOP()   No operation
#define RSND   4	// 1   1   ;Send_Command_Reg(reg)	 Send command R[reg] to SS 

#define TIM    8    // 1   1   ;Set_Timer(val)  Set counter value (us) for next IRQ3. val<16,777,215 [us]
#define LTIM   0xB  // 1   1   ;Set_Timer(val)  Set counter value (ms) for next IRQ3. val< 4,294,967 [ms]
#define RTIM   9    // 1   1   ;Set_TimerReg(reg) Set_Timer(R[reg])
//;#define READ   0xA  // 1   1   ;Read_HK_Reg(reg)   Store received HK in R[reg]
#define RINC   0x10 // 1   1   ;Increment_Register(reg) R[reg] = R[reg] + 1
#define RDEC   0x11 // 1   1   ;Decrement_Register(reg) R[reg] = R[reg] - 1
#define RSET   0x12 // 2   2   ;Set_Register(reg, val32) R[reg] = val32
#define RADD   0x13 // 2   2   ;Add_To_Register(reg, val32) R[reg] = R[reg] + val32
#define RSUB   0x14 // 2   2   ;Subtract_To_Register(reg, val32) R[reg] = R[reg] - val32
#define RMUL   0x15 // 2   2   ;Multiply_To_Register(reg, val32) R[reg] = R[reg] * val32
#define RDIV   0x16 // 2   2   ;Divide_To_Register(reg, val32) R[reg] = R[reg] / val32
#define RAND   0x18 // 2   2   ;And(reg, val32) R[reg] = R[reg] & val32
#define ROR    0x19 // 2   2   ;OR(reg, val32) R[reg] = R[reg] | val32
#define RSHR   0x1A // 2   1   ;Reg_Shift_Right(reg,val)  R[reg] >>= val
#define RSHL   0x1B // 2   1   ;Reg_Shift_Right(reg,val)  R[reg] <<= val
#define RREQ   0x20 // 2   1   ;Reg_Equate(reg1,reg2)  R[reg1] = R[reg2]
#define XREQ   0x1F // 2   1   ;Indx_Reg_Equate(reg1,reg2)  R[R[reg1]] = R[R[reg2]]
#define RRAD   0x21 // 3   1   ;Add_Register_To_Register(r1,r2,r3) R[r1]=R[r2]+R[r3]
#define RRSB   0x22 // 3   1   ;Sub_Register_To_Register(r1,r2,r3) R[r1]=R[r2]-R[r3]
#define RRMP   0x23 // 3   1   ;Mult_Register_To_Register(r1,r2,r3) R[r1]=R[r2]*R[r3]
#define RRDV   0x24 // 3   1   ;Div_Register_To_Register(r1,r2,r3) R[r1]=R[r2]/R[r3]
#define JMPR   0x30 // 1   1   ;Jmp_Relative(val)  PC = PC + val
#define RJPR   0x31 // 1   1   ;Jmp_Relative_Reg(reg)  PC = PC + R[reg]
#define JPNZ   0x32 // 2   1   ;JumpNZ(reg, val)   If (R[reg] !=0) PC = PC + val
#define RSZ    0x33 // 1   1   ;Skip_Reg_Zero(reg) If (R[reg] !=0) PC = PC + 1
#define RSGT   0x34 // 2   1   ;Skip_Reg_GT(reg1,reg2) If (R[reg1] > R[reg2]) PC = PC + 1
#define RSLT   0x35 // 2   1   ;Skip_Reg_LT(reg1,reg2) If (R[reg1] < R[reg2]) PC = PC + 1
#define CALL   0x40 // 1   1   ;Call_Subr(val) PC = val (remember the present PC)
#define RET    0x41 // 0   1   ;Return()   Return from subroutine
#define WRT    0x48 // 1   1   ;Write(reg) Write R[reg] to DPU HK
#define RMOV   0x49	// 2   1   ;Move_To_Reg(reg,[Addr]) R[reg]=val32[Addr]
#define RRMV   0x4A	// 2   1   ;Move_To_Reg(reg,[reg1]) R[reg]=val32[R[reg1]]
#define RSTO   0x4B	// 2   1   ;Store_From_Reg(reg,[Addr]) val32[Addr]=R[reg]
#define RRST   0x4C	// 2   1   ;Store_From_Reg(reg,[reg1]) val32[R[reg1]]=R[reg]
#define EVNT   0x53	// 2   1   ;Send_Event(EventNo, reg )Send event=EventNo with parameter R[reg]
#define END    0x50 // 0   1   ;End End current VM program
#define SVEV   0x56 // 1   1   ;set_Virtuoso_event(EventNo)
#define RSVEV  0x57 // 1   1   ;set_Virtuoso_event_From_Reg(reg)  Set Virtuoso event N. R[reg]

//; #define END    0x7F // 0   1   ;End End current VM program

#define EQU    0x101 // 1   1   ;Store at the current addr the constant parameter 
#define ORG    0x200 // 1	0	;Address of code
#define DEF    0x201 // 2	0	;Set constants (define NEWADD, 0x200)
#define INC    0x202 // 1	0	;Include source file
//;------------------------------------------------------
#define VAL32  0x100 // 1   1   ;is temporary reserved for 2nd instruction (val32)
#define TRST   0x208 // 0	0	;reset local timer in the simulator
#define COM	   0x209 // 0	0	;comments for the simulator
#define ROUT   0x20a // 0   0   ;print in the simulator the contents of the numbered registers R[]
#define TABLE  0x20b // 1   0   ;Define the VM table to use. 
#define NAME   0x20c // 1   0   ;Define the CLName. 
#define VERSION  0x20d // 1   0   ;Define the CLVersion. 
#define CVSID  0x20e // 1   0   ;Define the CLCVSId.
#define LABEL  0x300 //			; for addr. labels
                     //         ;in RSET RADD etc
#endif      //; HIFI_SYNTAX_H_