/**
 * MIL-STD 1553B Library - Carlo Gavazzi Space
 *
 * Filename             : \file MilIrq.h
 *
 * Purposes             : \brief MIL-STD 1553B Library - Carlo Gavazzi Space
 *
 * Logical Task         :
 *
 * Author               : CGSpace
 *
 * Last Developer       : $Author: lorenzo $
 *
 * Revision             : $Revision: 1.3
 *
 * Checkout Tag         : $Name:  $
 *
 * Last Modification    : $Date: 2006/10/20 09:22:14 $
 *
 * Location             : $RCSfile: MilIrq.h,v $
 *
 * \version             : $Header: /home/local/cvsrep/OBS_FM/1553_Lib/MilIrq.h,v 1.10 2006/10/20 09:22:14 lorenzo Exp $
 */
 
/*
 * Commitments History :
 * As reported in Main cvs Documentation
 * ( https://www.cvshome.org/docs/manual/cvs-1.11.18/cvs_12.html#SEC102 )
 * The Modification Log has been posted at End Of File.
 */

// ---------------------------------------------------------------------------//
/*	Milirq.h -   The routines in this module involve the control and servicing of
 * interrupt requests */

/*
 Purpose:	The module contains the routines for managing the ACE chip in
			RT mode.
 Content:	The module contains the following functions:
SUBHEADINGS
 Project        : HSO/FIRST BASIC S/W
 Component      : HSO/FIRST DRIVERS S/W
 Filename       : $RCSfile: MilIrq.h,v $ 
 CI Number      :
 Revision       : Revision: 1.3
 Company        : Carlo Gavazzi Space S.P.A.
 Author         : Andrea Bertoli
 Creation Date  : 2000/05/15
 Last ChangeDate: $Date: 2006/10/20 09:22:14 $

SEE ALSO: 
 ADD Ref: Inserted here reference with Architectural
			Design and Detail Document.
 Other Ref:
 Notes:
*/

#ifndef __MILIRQ__
#define __MILIRQ__

/* INTERRUPT CONSTANTS ----------------------------------------------------*/

/* IRQ status reg and IRQ mask reg */
#define IRQ_ALL                          0xffff
#define IRQ_MASTER                       0x8000
#define IRQ_RAM_PARITY_ERROR             0x4000
#define IRQ_TRANSMITTER_TIMEOUT          0x2000
#define IRQ_BC_RT_CMD_STK_ROLLOVR        0x1000
#define IRQ_MT_CMD_STACK_ROLLOVR         0x0800
#define IRQ_MT_DTA_STACK_ROLLOVR         0X0400
#define IRQ_HANDSHAKE_FAILURE            0X0200
#define IRQ_BC_RETRY                     0X0100
#define IRQ_RT_ADDR_PARITY_ERROR         0X0080
#define IRQ_TIMETAG_ROLLOVR              0X0040
#define IRQ_RT_CIRC_BUFFR_ROLLOVR        0X0020
#define IRQ_RT_BC_MESSAGE_INT            0X0010
#define IRQ_BC_END_OF_FRAME              0X0008
#define IRQ_RT_BC_MT_FORMAT_ERROR        0X0004
#define IRQ_STATUS_SET_MODE_INT_TRIG     0X0002
#define IRQ_END_OF_MESSAGE               0X0001

/* parameter for BuIrqType */
#define PULSE        0
#define LEVEL        1

/* INTERRUPT FUNCTION PROTOTYPES  -----------------------------------------*/

/* sets auto clear irq on read of irq status register */
MilError_t MilIrqAutoClear( MilConf_p pw_MilConf, unsigned char d_Selection);

/* sets irq line for level or pulse irq signal */
MilError_t MilIrqType( MilConf_p pw_MilConf, unsigned char d_Selection);

/* allows the enable of interrupt conditions */
MilError_t MilIrqEnable( MilConf_p pw_MilConf, unsigned int j_Mask);

/* allows the disable of interrupt conditions */
MilError_t MilIrqDisable( MilConf_p pw_MilConf, unsigned int j_Mask);

/* get interrupt register status */
unsigned int MilGetIrqStatus( MilConf_p pw_MilConf);

/* resets ace INT* output to a logic 1 */
MilError_t MilIrqReset( MilConf_p pw_MilConf);

#endif /* __MILIRQ__ */

 
// ---------------------------------------------------------------------------//
/*
 * modification history
 * --------------------
 * $Log: MilIrq.h,v $
 * Revision 1.10  2006/10/20 09:22:14  lorenzo
 * 1553 library updated
 *
 * Revision 1.7  2006/06/07 11:44:55  scige
 * Some More Comment
 * by Scige John Liu IFSI
 *
 * Revision 1.6  2006/04/27 10:21:44  scige
 * Some more Comment alignement before STRONG COMMENTING
 *
 * Revision 1.5  2006/02/15 14:56:57  scige
 * Abstract comment reformatted
 * History log replaced or moved at end of file
 */