/************************************************************************* $Archive: /pacs/OnBoard/mim.h $ $Revision: 1.14 $ $Date: 2009/04/23 13:51:12 $ $Author: amazy $ $Log: mim.h,v $ Revision 1.14 2009/04/23 13:51:12 amazy 6.029 * * 10 11/06/08 5:17p Pacs1 * mech move now triggered again on the shifted sync * * 9 10/09/08 10:17p Pacs1 * * 8 30/09/08 15:19 Amazy * - increased grating power limit to 150mA and made it commandable * - added a synchro counter in HK * - new parameters value for DMC_SYNCHRONIZE_ON_DET to avoid using the * synchro to trigger the mechanisms move * - In photo, the RedSpuTransmission mode was not copied into red science * headers. It is now corrected * * 7 6/04/08 11:45p Amazy * - added a filter to the grating controller * - now resetting ChopperOut in the chopper enable * * 6 6/07/07 11:01a Amazy * v6.018 * * 5 5/31/07 11:27a Amazy * v6.018 * * 51 3/14/06 4:32p Pacs Egse * Version 6.001 * Cleaned and commented *************************************************************************/ #define MIM_H #ifndef INCLUDE_DEFINE_ONLY //used when included from assembly code #ifndef CSL_TYPE_H #include "csl_type.h" #endif extern void WriteFpgaRegisters(); extern void InitializeFpgaParameters(); extern void InitializeMimParameters(); extern int gHallSensorA; extern int gHallSensorB; extern int gCalSrcDacLatch; /* STRUCT : HkAnalogMeasures ************************* AUTHOR : AMazy USE : This structure contains all the analog measures that are acquired in the ISR. */ typedef struct { int Spares1[1]; int PowerSupplyVoltagePos5V; int PowerSupplyV1Current; int FWSpecPosASensor; int FWGratAmplifierVoltageA; int ChopperAmplifierVoltageA; int MecDCDCTemperature; int MecDSPTemperature; int SpuSWLTemp; int PowerSupplyVoltagePos15V; int PowerSupplyV2Current; int FWSpecPosBSensor; int FWGratAmplifierCurrentA; int ChopperAmplifierCurrentA; int SpuVccCurrent; int SpuP15V; int SpuLWLTemp; int PowerSupplyVoltageNeg15V; int PowerSupplyV3Current; int FWPhotoPosASensor; int FWGratAmplifierVoltageB; int ChopperAmplifierVoltageB; int ADCVoltage; int FWGratAmplifierCurrentB; int SpuPowerSupplyTemperature; int PowerSupplyVoltagePos28V; int PowerSupplyV4Current; int FWPhotoPosBSensor; int GratingLaunchLockMotorCurrent; int SpuVccVoltage; int RefVoltage5V; int SpuVpCurrent; int RefVoltage0V; int TempSensorsSrc1CurrentHighGain; int TempSensorsSrc1CurrentLowGain; int ChopperTemperatureSensorVoltage; int BB1TemperatureSensorVoltage; int FpuTemperatureSensor1Voltage; int FpuTemperatureSensor2Voltage; int TempSensorsSrc2VoltageNeg; /*reference voltage*/ int TempSensorsSrc2VoltagePos; /*reference voltage*/ int TempSensorsSrc2CurrentHighGain; int TempSensorsSrc2CurrentLowGain; int GratingTemperatureSensorVoltage; int FWSpecTemperatureSensorVoltage; int FWPhotoTemperatureSensorVoltage; int Spare4; int TempSensorsSrc1VoltageNeg; /*reference voltage*/ int TempSensorsSrc1VoltagePos; /*reference voltage*/ int Spares2[15]; //such that we have a total of 64 variables } HkAnalogMeasures; /* STRUCT : MimParameters ********************** AUTHOR : AMazy USE : This structure contains all information related to the MIM boards. This includes: - analog hk measures, - FPGA status - temporary variables for PID */ typedef struct MimParameters { int ReadoutCountInChopperPosition; //READOUT_COUNT uint IsrCount; //ISR_COUNT int IsrStat; //ISR_STAT int SyncCount; //SYNC_COUNT int PeriodCount; //PERIOD_COUNT int ControlWord; //CONTROL_WORD int StatusWord; //STATUS_WORD HkAnalogMeasures HkAnalogMeasures; int GratErrorT_0; int GratErrorT_1; float Freq; float Divisor; float ChopperPreviousPosition; float ChopperCurrentPosition; float ChopperPreviousError; float ChopperCurrentError; float ChopperAveragedSpeed; float ChopperAveragedOutput; float ChopperSpare1; float ChopperSpare2; float ChopperSpare3; float ChopperSpare4; float ChopperSpare5; float GratingPreviousCommand; float GratingPreviousError; float GratingCurrentCommand; float GratingCurrentError; int GratFwDAC1; int GratFwDAC2; float ChopperAveragedDError; float ChopperOut; float ChopperPrev1Out; float ChopperPrev2Out; float ChopperPrev3Out; float ChopperPrev4Out; float ChoppperFilterOut; float ChoppperFilterPrev1Out; float ChoppperFilterPrev2Out; float ChoppperFilterPrev3Out; float ChoppperFilterPrev4Out; int GratPrevPos; int GratPosCarry; int GratCurPos; float GratAveragedDError; float GratAveragedError; int InductosynPeriodJumpCarry; int InductosynReadout; int GratTempPos; float GratingOut; float GratingPrev1Out; float GratingPrev2Out; float GratingPrev3Out; float GratingPrev4Out; float GratingFilterOut; float GratingFilterPrev1Out; float GratingFilterPrev2Out; float GratingFilterPrev3Out; float GratingFilterPrev4Out; int MechanismsUseSynchro; } MimParameters; /* STRUCT : FpgaParameters *********************** AUTHOR : AMazy USE : All the parameters that can be sent to the Timing FPGA. There are temporary variables used by the 'write' command. These temporary values are copied in the final variables when the DMC_SET_TIMING_FPGA_PAR command is received */ typedef struct FpgaParameters { int SynchroSourceSelection; //0 = connect to output of pd4_reg ( simulated DEC SYNC nominal 256 Hz ), 1 = red DEC odd module, 2 = red DEC even module, 3 = blue DEC odd module, 4 = blue DEC even module , 5 = BOLC readout sync, 6 = connect to output of pd1_reg ( simulated BOLC SYNC nominal 40 Hz ), 7 = connect to test input ( only for ground ) int PhaseShiftRegister; // initial value = 0 int BolcFrequencyDivider; // is actually the (divider-1) int ProgrammableDivider5; int PhaseIncrement; int ControlRegister; //bit 0 = flag0_control ( 1 = output active ), bit 1 = start counter ( 1 = reset and start period counting ), bit 2 = master_reset ( 1 = DEC master reset ), bit 3 = reset PLL ( 1 = attempt to lock to OBT ) int TemporarySynchroSourceSelection; int TemporaryPhaseShiftRegister; int TemporaryBolcFrequencyDivider; int TemporaryProgrammableDivider5; int TemporaryPhaseIncrement; int TemporaryControlRegister; } FpgaParameters; /* STRUCT : TemperatureSensorsTask ******************************* AUTHOR : AMazy USE : This structure contains all the variables related to the Temperature sensor task */ typedef struct TemperatureSensorsTask { int TaskStatus; int CurrentPWM; int ControlWord; int MeasuresStatus[7]; int HighOrLowGain[7]; int TempMeasures[7]; int PosVoltages[7]; int NegVoltages[7]; int PosCurrents[7]; int NegCurrents[7]; int HkHighOrLowGain; int ChopperTemperatureSensorResistorValue; int BB1TemperatureSensorResistorValue; int FpuTemperatureSensor1ResistorValue; int FpuTemperatureSensor2ResistorValue; int GratingTemperatureSensorResistorValue; int FWSpecTemperatureSensorResistorValue; int FWPhotoTemperatureSensorResistorValue; } TemperatureSensorsTask; /* STRUCT : Temperature Sensors Status *********************************** AUTHOR : AMazy USE : Defines the status of a temperature sensor */ enum { TEMP_SENS_NOT_MEASURED, TEMP_SENS_TO_BE_MEASURED, TEMP_SENS_MEASURED, TEMP_SENS_ERROR }; /* STRUCT : Temperature Sensors Gain ********************************* AUTHOR : AMazy USE : Defines the two gains that can be used to measure the current in a temperature sensor. */ enum { TEMP_SENS_HIGH_GAIN, TEMP_SENS_LOW_GAIN }; #define K_BMASK_TEMP_SENS_HK_STATUS_INVALID 0x00000000 #define K_BMASK_TEMP_SENS_HK_STATUS_HIGH_GAIN 0x00000002 #define K_BMASK_TEMP_SENS_HK_STATUS_LOW_GAIN 0x00000001 #define K_BMASK_TEMP_SENS_HK_STATUS_ERROR 0x00000003 #define K_BMASK_TEMP_SENS_HK_STATUS 0x00000003 #endif //INCLUDE_DEFINE_ONLY /************************************************************************/ /* All the defines below define offset that shall be used in assembly */ /* code to access the C variables */ /* THESE REGISTERS ARE BELOW HK ARRAY AND SHOULD BE ADDRESSED VIA i6 */ /************************************************************************/ #define READOUT_COUNT -7 /* Readout counter in current chopper position*/ #define ISR_COUNT -6 /* ISR activation counter copy */ #define ISR_STAT -5 /* bit 0 = sync detect ( 1 period duration ) */ /* bit 1 = sync signal ( reset by high level ) */ #define SYNC_COUNT -4 /* SYNC counter */ #define PERIOD_COUNT -3 /* copy of timing FPGA period counter at SYNC time */ #define CONTROL_WORD -2 /* 16 LSB = hardware control register */ #define STATUS_WORD -1 /* 16 LSB = hardware status register 16 MSB = FPGA status */ /**********************************************************************/ /* These registers are inside HK ARRAY and should be addressed via i6 */ /**********************************************************************/ #define FW_SPEC_POSA 3 #define FW_SPEC_POSB 11 #define FW_PHOTO_POSA 19 #define FW_PHOTO_POSB 27 /*********************************************************************/ /* These registers are above HK ARRAY and should be addressed via i6 */ /*********************************************************************/ #define GRAT_ERRORT_0 64 #define GRAT_ERRORT_1 65 #define FREQ 66 #define DIVISOR 67 #define CHOP_PREV_POS 68 #define CHOP_CUR_POS 69 #define CHOP_PREV_ERR 70 #define CHOP_CUR_ERR 71 #define CHOP_AVG_SPEED 72 #define CHOP_AVG_OUT 73 #define CHOP_SPARE_1 74 #define CHOP_SPARE_2 75 #define CHOP_SPARE_3 76 #define CHOP_SPARE_4 77 #define CHOP_SPARE_5 78 #define GRAT_PREV_COM 79 #define GRAT_PREV_ERR 80 #define GRAT_CUR_COM 81 #define GRAT_CUR_ERR 82 #define GRAT_FW_DAC1 83 #define GRAT_FW_DAC2 84 #define CHOP_AVG_DERROR 85 #define CHOP_OUT 86 #define CHOP_PREV1_OUT 87 #define CHOP_PREV2_OUT 88 #define CHOP_PREV3_OUT 89 #define CHOP_PREV4_OUT 90 #define CHOP_FILTER_OUT 91 #define CHOP_FILTER_PREV1_OUT 92 #define CHOP_FILTER_PREV2_OUT 93 #define CHOP_FILTER_PREV3_OUT 94 #define CHOP_FILTER_PREV4_OUT 95 #define GRAT_PREV_POS 96 #define GRAT_POS_CARRY 97 #define GRAT_CUR_POS 98 #define GRAT_AVG_DERROR 99 #define GRAT_AVG_ERROR 100 #define GRAT_PER_CAR 101 #define GRAT_IND_READ 102 #define GRAT_TEMP_POS 103 #define GRAT_OUT 104 #define GRAT_PREV1_OUT 105 #define GRAT_PREV2_OUT 106 #define GRAT_PREV3_OUT 107 #define GRAT_PREV4_OUT 108 #define GRAT_FILTER_OUT 109 #define GRAT_FILTER_PREV1_OUT 110 #define GRAT_FILTER_PREV2_OUT 111 #define GRAT_FILTER_PREV3_OUT 112 #define GRAT_FILTER_PREV4_OUT 113 #define MECH_USES_SYNCHRO 114 /**************************************************************** MIM and TIMING FPGA registers definition ****************************************************************/ //Note : //W = write only //R = read only #define TIMING_PD1 0x20040080 //not used since 01/05/04 #define TIMING_PD2 0x20040081 //not used since 01/05/04 #define TIMING_PD3 0x20040082 //not used since 01/05/04 #define TIMING_PD4 0x20040083 //not used since 01/05/04 #define TIMING_SYNC_SRC 0x20040084 //W 3bits synchro source selection #define TIMING_PHASE_SHIFT 0x20040085 //W 14bits #define TIMING_PERIOD 0x20040086 //R 32bits #define TIMING_CTRL_REG 0x20040087 //W #define TIMING_STATUS 0x20040088 //R #define TIMING_PHASE_INC 0x20040089 //W #define TIMING_RES_LO 0x2004008A //R #define TIMING_RES_HI 0x2004008B //R #define TIMING_PD5 0x2004008C //W #define MIM_CHOP_POS_AND_HK 0x20040041 //R 16msb : chopper pos, 16lsb : hk #define MIM_HALL_SENSORS 0x20040040 //R 2x16bits for each hall sensor ADC #define MIM_STATUS_REG 0x20040042 //R #define MIM_INDUCTOSYN 0x20040043 //R 24lsb : grating position, bit24 : busy signal from AD2S80 #define MIM_READBACK 0x20040044 //R copy of the last written register value (actually not implemented) #define MIM_CTRL_REG 0x20040045 //W #define MIM_CHOPPER_DAC 0x20040046 //W 16bits (FPGA inverts sign bit) #define MIM_GRAT_FW_DAC1 0x20040047 //W 16bits (FPGA inverts sign bit) #define MIM_GRAT_FW_DAC2 0x20040048 //W 16bits (FPGA inverts sign bit) #define MIM_CS1_DAC 0x20040049 //W 16bits (FPGA inverts sign bit) #define MIM_CS2_DAC 0x2004004A //W 16bits (FPGA inverts sign bit) #define MIM_CS_ADC 0x2004004A //R 16 lsb #define TIMING_MUX 0x2004004A //R 16 msb #define MIM_GRAT_FW_DACWRT 0x2004004B //W mandatory writing after GRAT_FW_DAC writing #define MIM_CHOPPER_DACWRT 0x2004004C //W mandatory writing after CHOPPER_DAC writing #define MIM_CS_LATCH 0x2004004D //W copy CS1 and CS2 DAC to outputs + latch 8 bits of analog mux address to be set by ChopGrat.s (actually not implemented) #define HK_TEST 0x2004004E //W 16bits (actually not implemented) #define HK_PWM 0x2004004E //W 10bits // MIM control word bit fields #define K_BMASK_MIM_HK_MUX_SELECT_GRATING 0x00000000 #define K_BMASK_MIM_HK_MUX_SELECT_FW_SPEC 0x00000001 //(FW_SPEC = FW_1) #define K_BMASK_MIM_HK_MUX_SELECT_FW_PHOTO 0x00000002 //(FW_PHOTO = FW_2) #define K_BMASK_MIM_HK_MUX_SELECT_MASK 0x00000003 #define K_BMASK_MIM_CHOPPER_POWER_ON 0x00000004 #define K_BMASK_MIM_CHOPPER_POWER_OFF 0x00000000 #define K_BMASK_MIM_CHOPPER_POWER_CONTROL 0x00000004 #define K_BMASK_MIM_CHOPPER_COIL_MODE_MASK 0x00000078 #define K_BMASK_MIM_CHOPPER_COIL_NOMINAL 0x00000028 #define K_BMASK_MIM_CHOPPER_COIL_DEGRADED 0x00000050 #define K_BMASK_MIM_DRIVE_SELECT_GRATING 0x00000000 #define K_BMASK_MIM_DRIVE_SELECT_FW_SPEC 0x00000080 #define K_BMASK_MIM_DRIVE_SELECT_FW_PHOTO 0x00000180 #define K_BMASK_MIM_DRIVE_SELECT_MASK 0x00000180 #define K_BMASK_MIM_INDUCTOSYN_POWER_ON 0x00000200 #define K_BMASK_MIM_INDUCTOSYN_POWER_OFF 0x00000000 #define K_BMASK_MIM_INDUCTOSYN_POWER_CONTROL 0x00000200 #define K_BMASK_MIM_GRATING_LAUNCH_LOCK 0x00000400 #define K_BMASK_MIM_GRATING_LAUNCH_UNLOCK 0x00000800 #define K_BMASK_MIM_GRATING_LAUNCH_LOCK_OFF 0x00000000 #define K_BPOS_MIM_GRATING_LAUNCH_LOCK 10 #define K_BPOS_MIM_GRATING_LAUNCH_UNLOCK 11 #define K_BPOS_MIM_GRATING_IND_AMP 12 //PWM command for inductosyn amplitude adjustment #define K_BMASK_MIM_GRATING_LAUNCH_LOCK2 0x00200000 #define K_BMASK_MIM_GRATING_LAUNCH_UNLOCK2 0x00100000 #define K_BMASK_MIM_GRATING_LAUNCH_LOCK_OFF2 0x00000000 #define K_BPOS_MIM_GRATING_LAUNCH_LOCK2 21 #define K_BPOS_MIM_GRATING_LAUNCH_UNLOCK2 20 #define K_BMASK_MIM_GRATING_LAUNCH_LOCK_MASK 0x00300c00 #define K_BMASK_MIM_ISR_EXECUTING 0x00002000 #define K_BPOS_MIM_ISR_EXECUTING 13 #define K_BMASK_MIM_BLUE_DEC_POWER_ON 0x00004000 #define K_BMASK_MIM_BLUE_DEC_POWER_OFF 0x00000000 #define K_BMASK_MIM_BLUE_DEC_POWER_CONTROL 0x00004000 #define K_BMASK_MIM_RED_DEC_POWER_ON 0x00008000 #define K_BMASK_MIM_RED_DEC_POWER_OFF 0x00000000 #define K_BMASK_MIM_RED_DEC_POWER_CONTROL 0x00008000 // timing FPGA control / status word bit definitions ( direct access to hardware ) // register address is FPGA_STATUS defined above #define K_BPOS_TIMING_FLAG0_ENB 0 /* test output on front panel */ #define K_BPOS_TIMING_COUNT_ENB 1 /* enables hardware OBT counter and software sync counter */ #define K_BPOS_TIMING_MASTER_RESET 2 /* master reset for the DECs */ #define K_BPOS_TIMING_RESET_PLL 3 /* restarts OBT locking attempt */ #define K_BPOS_TIMING_PLL_PD_SYNC 4 /* special mode where divider chain restarts on sync */ #define K_BPOS_TIMING_OBT_DISABLE 5 /* special mode OBT lock disabled ( PLL free running ) */ #define K_BPOS_TIMING_OBT_MISSING 6 /* status bit lock on OBT failed */ #define K_BPOS_TIMING_PERIOD_COUNT_RESET 6 #define K_BPOS_TIMING_OBT_OVR 7 /* status bit OBT frequency too high (obsolete) */ #define K_BPOS_TIMING_SYNC_SRC_SEL 8 /* unshifted sync signal from selector lasts one SAMPLE */ #define K_BPOS_TIMING_SYNC_PRESENT 9 /* shifted sync signal from selector (reset after reading) */ #define K_BPOS_TIMING_SAMPLE_IN 10 #define K_BPOS_TIMING_PERIOD_COUNT_RESET_ACK 11 /* acknowledges a K_BPOS_TIMING_PERIOD_COUNT_RESET*/ #define K_BPOS_TIMING_BOLC_INPUT_OFF 12 #define K_BPOS_TIMING_BOLC_MISSING 13 /* not implemented */ #define K_BPOS_TIMING_MUXADR_CHOICE_0 15 #define K_BPOS_TIMING_MUXADR_CHOICE_1 16 #define K_BPOS_TIMING_HK_ENB 22 #define K_BPOS_TIMING_HK_NDIV25 23 #define K_BPOS_TIMING_HK_POSNEG 24 #define K_BMASK_TIMING_COUNT_ENB 0x00000002 #define K_BMASK_TIMING_MASTER_RESET 0x00000004 #define K_BMASK_TIMING_HK_ENB 0x00400000 #define K_BMASK_TIMING_HK_NDIV25 0x00800000 #define K_BMASK_TIMING_HK_POSNEG 0x01000000 #define K_BMASK_TIMING_HK 0x01C00000 #define K_BMASK_TIMING_ACCESSIBLE_BITS 0x001E003A #define K_BMASK_TIMING_ISR_FREG_LSB 0x00020000 #define K_BMASK_TIMING_ISR_FREG_MSB 0x00040000 #define K_BMASK_TIMING_MUXADR_GRATING 0x00000000 #define K_BMASK_TIMING_MUXADR_FWSPEC 0x00008000 #define K_BMASK_TIMING_MUXADR_FWPHOTO 0x00010000 #define K_BMASK_TIMING_MUXADR 0x00018000 // ISR_STAT software status bits ( set by ISR routine ) #define K_BPOS_MIM_SYNC_STATUS 0 /* real time status, lasts one sample period */ #define K_BPOS_MIM_SYNC_FLAG 1 /* signal set by ISR, (is reset by high level software every 2 seconds to signal missing synchro) */ #define K_BPOS_MIM_SHIFTED_SYNC_FLAG 2 /* shifted sync, lasts one sample period */ #define K_BMASK_MIM_SYNC_FLAG 0x00000007 // STATUS_WORD bits ( set by ISR routine, copies of actual hardware inputs updated at 8 KHz ) #define K_BPOS_MIM_STATUS_HK_INDEX 0 // first bit of hk index #define K_BLEN_MIM_STATUS_HK_INDEX 6 #define K_BPOS_MIM_STATUS_GRATING_LAUNCH_LOCKED 10 // set to 1 when LL in locked position #define K_BPOS_MIM_STATUS_GRATING_LAUNCH_UNLOCKED 11 // set to 1 when LL in unlocked position #define K_BPOS_MIM_STATUS_GRATING_LIMIT_SWITCH 12 // set to 1 when LSW is pressed // COPIES OF TIMING FPGA STATUS BITS IN STATUS_WORD (set by ISR routine) #define K_BPOS_TIMING_OBT_MISSING_ST 22 /* status bit lock on OBT failed */ #define K_BPOS_TIMING_OBT_OVR_ST 23 /* status bit OBT frequency too high */ // CALIBRATION SOURCE HARDWARE STATUS BITS ( MULTIPLEXER ADDRESSES ) #define K_BMASK_CS_CHANNEL_INDEX 0x70000000 #define K_BPOS_CS_CHANNEL_INDEX 28 #define K_BLEN_CS_CHANNEL_INDEX 3 #define K_BMASK_CS_MUXADR 0x7FF80000 #define K_BPOS_CS_MUXADR 19 #define K_BLEN_CS_MUXADR 12 #define K_BMASK_GR_INDUC_MUXADR 0x3FFC0000 #define K_BPOS_GR_INDUC_MUXADR 18 #define K_BLEN_GR_INDUC_MUXADR 12 #define K_BPOS_CS_MUXADR8 24 #define K_BPOS_CS_MUXADR11 27 #define K_BPOS_CS_MUXADR12 28 #define K_BPOS_CS_MUXADR13 29 #define K_BPOS_CS_MUXADR14 30