/*************************************************************************
$Archive: /pacs/OnBoard/mim.c $
$Revision: 1.15 $  $Date: 2009/04/23 13:51:12 $  
$Author: amazy $ 
$Log: mim.c,v $
Revision 1.15  2009/04/23 13:51:12  amazy
6.029

 * 
 * 13    10/09/08 10:17p Pacs1
 * 
 * 12    30/09/08 15:19 Amazy
 * - increased grating power limit to 150mA and made it commandable
 * - added a synchro counter in HK
 * - new parameters value for DMC_SYNCHRONIZE_ON_DET to avoid using the
 * synchro to trigger the mechanisms move
 * - In photo, the RedSpuTransmission mode was not copied into red science
 * headers.  It is now corrected
 * 
 * 11    6/04/08 11:45p Amazy
 * - added a filter to the grating controller
 * - now resetting ChopperOut in the chopper enable
 * 
 * 10    6/07/07 11:01a Amazy
 * v6.018
 * 
 * 9     5/31/07 11:27a Amazy
 * v6.018
 * 
 * 8     15/01/07 16:35 Amazy
 * 
 * 7     15/01/07 15:05 Amazy
 * 
 * 6     15/01/07 15:04 Amazy
 * in WriteFpgaRegisters, the duration allowed at max output for the
 * grating was around 600ms instead of 5s
 * 
 * 46    3/14/06 4:32p Pacs Egse
 * Version 6.001
 * Cleaned and commented
*************************************************************************/

#ifdef SIMULATOR
#include "virtuosoSim.h"
#else // SIMULATOR
#include "v_macro.h"
#include "node1.h"
#include "k_struct.h"
#endif

#include "seq.h"
#include "params.h"


//****************************************************************
// GLOBAL PARAMETERS
//****************************************************************

// internal storage for isr
int gHallSensorA;
int gHallSensorB;
int gCalSrcDacLatch = 0;

//****************************************************************
// FUNCTION IMPLEMENTATION
//****************************************************************

/*
CMD_FUNCTION : BOOL CommandSetTimingFpgaParameters(CommandParameter paramNotUsed)
*********************************************************************************

AUTHOR : Amazy

USE :
Command that writes the timing FPGA parameters in the FPGA.
The parameters must have been uploaded before through a write command
*/
BOOL CommandSetTimingFpgaParameters(CommandParameter paramNotUsed)
{
	//copy the temporary paremeters into the final paremeters
//	gpFPGA->SynchroSourceSelection	= gpFPGA->TemporarySynchroSourceSelection;		this parameter is now only accessible through the trigger command DMC_SYNCHRONIZE_ON_DET
	gpFPGA->PhaseShiftRegister		= gpFPGA->TemporaryPhaseShiftRegister;		
	gpFPGA->BolcFrequencyDivider	= gpFPGA->TemporaryBolcFrequencyDivider;		
	gpFPGA->ProgrammableDivider5	= gpFPGA->TemporaryProgrammableDivider5;	
	gpFPGA->PhaseIncrement			= gpFPGA->TemporaryPhaseIncrement;		
	SET_BITS(gpFPGA->ControlRegister, K_BMASK_TIMING_ACCESSIBLE_BITS, gpFPGA->TemporaryControlRegister)
	
	//write the FPGA paremeters
	WriteFpgaRegisters();

	SequencerSendAck(DMC_SET_TIMING_FPGA_PAR);
	return TRUE;
}

/*
FUNCTION : void WriteFpgaRegisters()
************************************

AUTHOR : Amazy

USE :
Writes the timing FPGA parameters in the FPGA.
The parameters must have been uploaded before through a write command
*/
void WriteFpgaRegisters()
{
#ifndef SIMULATOR
	*((int*)TIMING_PD5) = gpFPGA->ProgrammableDivider5;
	__asm(" nop;nop;nop;nop;nop;nop;nop; ");
	*((int*)TIMING_SYNC_SRC) = gpFPGA->SynchroSourceSelection;
	__asm(" nop;nop;nop;nop;nop;nop;nop; ");
	*((int*)TIMING_PHASE_SHIFT) = gpFPGA->PhaseShiftRegister;
	__asm(" nop;nop;nop;nop;nop;nop;nop; ");
	*((int*)TIMING_PHASE_INC) = gpFPGA->PhaseIncrement;
	__asm(" nop;nop;nop;nop;nop;nop;nop; ");
	*((int*)TIMING_CTRL_REG) = gpFPGA->ControlRegister;
#endif // not def SIMULATOR

	//the ISR frequency might have been affected by this modification
	//keep the time-out for grating max output at around 5s  whatever the ISR frequency is.
	if (TEST_ONE_BIT(gpFPGA->ControlRegister, K_BMASK_TIMING_ISR_FREG_LSB))
	{
		if (TEST_ONE_BIT(gpFPGA->ControlRegister, K_BMASK_TIMING_ISR_FREG_MSB))
		{
			gpGratingController->NbInterruptsBeforeStoppingOutput = 8*640;
			gpMim->Freq	= 1024.0f;			
		}
		else
		{
			gpGratingController->NbInterruptsBeforeStoppingOutput = 8*2560;
			gpMim->Freq	= 4096.0f;			
		}
	}
	else
	{
		if (TEST_ONE_BIT(gpFPGA->ControlRegister, K_BMASK_TIMING_ISR_FREG_MSB))
		{
			gpGratingController->NbInterruptsBeforeStoppingOutput = 8*1280;
			gpMim->Freq	= 2048.0f;			
		}
		else
		{
			gpGratingController->NbInterruptsBeforeStoppingOutput = 8*5120;
			gpMim->Freq	= 8192.0f;			
		}
	}
	gpGratingController->CurrentNbInterruptsOfMaxOutput = 0;

	if (TEST_ONE_BIT(gpFPGA->ControlRegister, 0x20))	//this means PLL is synchronized on BOLC
	{
		gpMim->Freq = 8320.0f;
	}
}

/*
FUNCTION : void InitializeFpgaParameters()
******************************************

AUTHOR : Amazy

USE :
Initializes the timing FPGA parameters with default values
*/
void InitializeFpgaParameters()
{
	gpFPGA->SynchroSourceSelection	=	0;
	gpFPGA->PhaseShiftRegister		=	0;
	gpFPGA->BolcFrequencyDivider	=	0;
	gpFPGA->ProgrammableDivider5	=	0x1A;
	gpFPGA->PhaseIncrement			=	0x095217CB; 
	gpFPGA->ControlRegister			=	0xB;  

	gpFPGA->TemporarySynchroSourceSelection	=	0;
	gpFPGA->TemporaryPhaseShiftRegister		=	0;
	gpFPGA->TemporaryBolcFrequencyDivider	=	0;
	gpFPGA->TemporaryProgrammableDivider5	=	0x1A;
	gpFPGA->TemporaryPhaseIncrement			=	0x095217CB; 
	gpFPGA->TemporaryControlRegister		=	0xB;
}

/*
FUNCTION : void InitializeMimParameters()
*****************************************

AUTHOR : Amazy

USE :
Initializes the MIM parameters.
These parameters are used by the various mechanisms controllers inside the ISR.
*/
void InitializeMimParameters()
{
	gpMim->ControlWord = 0;
	gpMim->GratErrorT_0	= 0;		
	gpMim->GratErrorT_1	= 0;		
	gpMim->Freq	= 8192.0f;			
	gpMim->Divisor = 1000.0f;		
	gpMim->ChopperPreviousPosition = 0.0f;
	gpMim->ChopperCurrentPosition = 0.0f;
	gpMim->ChopperPreviousError	= 0.0f;
	gpMim->ChopperCurrentError = 0.0f;
	gpMim->ChopperAveragedSpeed	= 0.0f;
	gpMim->ChopperAveragedOutput = 0.0f;
	gpMim->ChopperAveragedDError = 0.0f;
	gpMim->ChopperOut = 0.0f;
	gpMim->ChopperPrev1Out = 0.0f;
	gpMim->ChopperPrev2Out = 0.0f;
	gpMim->ChopperPrev3Out = 0.0f;
	gpMim->ChopperPrev4Out = 0.0f;
	gpMim->ChoppperFilterOut = 0.0f;
	gpMim->ChoppperFilterPrev1Out = 0.0f;
	gpMim->ChoppperFilterPrev2Out = 0.0f;
	gpMim->ChoppperFilterPrev3Out = 0.0f;
	gpMim->ChoppperFilterPrev4Out = 0.0f;
	gpMim->GratFwDAC1 = 0x0;
	gpMim->GratFwDAC2 = 0x0;
	gpMim->GratPrevPos = 0;
	gpMim->GratCurPos = 0;
	gpMim->GratPosCarry = 0;
	gpMim->GratingPreviousError = 0;
	gpMim->GratAveragedDError = 0.0f;
	gpMim->GratAveragedError = 0.0f;
	gpMim->GratingOut = 0.0f;
	gpMim->GratingPrev1Out = 0.0f;
	gpMim->GratingPrev2Out = 0.0f;
	gpMim->GratingPrev3Out = 0.0f;
	gpMim->GratingPrev4Out = 0.0f;
	gpMim->GratingFilterOut = 0.0f;
	gpMim->GratingFilterPrev1Out = 0.0f;
	gpMim->GratingFilterPrev2Out = 0.0f;
	gpMim->GratingFilterPrev3Out = 0.0f;
	gpMim->GratingFilterPrev4Out = 0.0f;
	gpMim->MechanismsUseSynchro = 1;
}