/************************************************************************* $Archive: /PACS/OnBoard/m_smcsge.h $ $Revision: 1.10 $ $Date: 2009/04/23 13:51:12 $ $Author: amazy $ $Log: m_smcsge.h,v $ Revision 1.10 2009/04/23 13:51:12 amazy 6.029 * * 4 28/08/02 11:49 Amazy * Added the header with the history log *************************************************************************/ /***************************************************************************** * * Project name: Herschel PACS DEC-MEC * Product name: DM_LLDRV * Object name: m_smcsge * Filename: %M% * Language: C (ADSP-21020) * Compiler: G21K - r3.3 * Company: CRISA * Author: F. Torrero * Version: %I% * Creation date: 22/Mar/2002 * Last Modification date: %G% * * Description =============================================================== * * This module implements the lowest level functions and general definitions * related to management of two SMCS chips * * Change log =============================================================== * * | DATE | NEW VERSION | AUTHOR | REASON FOR CHANGE | * =========================================================================== * * 22/Mar/02 1 F.Torrero Creation * * ****************************************************************************/ #ifndef M_SMCSGE_H #define M_SMCSGE_H /***************************************************************************** INCLUDES *****************************************************************************/ #include "l_gendef.h" #include "l_hwmap.h" /***************************************************************************** PROVIDED CONSTANTS *****************************************************************************/ /* SMCS chips */ #define K_SMCS_1 1 #define K_SMCS_2 2 /* Data Memory SMCS chips register addresses */ #define K_DMADD_SMCS1_SICR K_DMADDR_BASE_SMCS1 + 0x00 #define K_DMADD_SMCS1_TRS_CTRL K_DMADDR_BASE_SMCS1 + 0x01 #define K_DMADD_SMCS1_RT_CTRL K_DMADDR_BASE_SMCS1 + 0x02 #define K_DMADD_SMCS1_ISR K_DMADDR_BASE_SMCS1 + 0x04 #define K_DMADD_SMCS1_IMR K_DMADDR_BASE_SMCS1 + 0x08 #define K_DMADD_SMCS1_COMI_CS0R K_DMADDR_BASE_SMCS1 + 0x0C #define K_DMADD_SMCS1_COMI_ACR K_DMADDR_BASE_SMCS1 + 0x0E #define K_DMADD_SMCS1_PRCIR K_DMADDR_BASE_SMCS1 + 0x0F #define K_DMADD_SMCS1_CH1_DSM_MODR K_DMADDR_BASE_SMCS1 + 0x10 #define K_DMADD_SMCS1_CH1_DSM_CMDR K_DMADDR_BASE_SMCS1 + 0x11 #define K_DMADD_SMCS1_CH1_DSM_STAR K_DMADDR_BASE_SMCS1 + 0x12 #define K_DMADD_SMCS1_CH1_DSM_TSTR K_DMADDR_BASE_SMCS1 + 0x13 #define K_DMADD_SMCS1_CH1_ADDR K_DMADDR_BASE_SMCS1 + 0x14 #define K_DMADD_SMCS1_CH1_RT_ADDR K_DMADDR_BASE_SMCS1 + 0x15 #define K_DMADD_SMCS1_CH1_PR_STAR K_DMADDR_BASE_SMCS1 + 0x16 #define K_DMADD_SMCS1_CH1_CNTRL1 K_DMADDR_BASE_SMCS1 + 0x18 #define K_DMADD_SMCS1_CH1_CNTRL2 K_DMADDR_BASE_SMCS1 + 0x19 #define K_DMADD_SMCS1_CH1_HTID K_DMADDR_BASE_SMCS1 + 0x1A #define K_DMADD_SMCS1_CH1_HCNTRL K_DMADDR_BASE_SMCS1 + 0x1B #define K_DMADD_SMCS1_CH1_ESR1 K_DMADDR_BASE_SMCS1 + 0x1C #define K_DMADD_SMCS1_CH1_ESR2 K_DMADDR_BASE_SMCS1 + 0x1D #define K_DMADD_SMCS1_CH1_COMICFG K_DMADDR_BASE_SMCS1 + 0x1F #define K_DMADD_SMCS1_CH1_TX_SAR K_DMADDR_BASE_SMCS1 + 0x20 #define K_DMADD_SMCS1_CH1_TX_EAR K_DMADDR_BASE_SMCS1 + 0x22 #define K_DMADD_SMCS1_CH1_TX_CAR K_DMADDR_BASE_SMCS1 + 0x24 #define K_DMADD_SMCS1_CH1_TX_EOPB K_DMADDR_BASE_SMCS1 + 0x27 #define K_DMADD_SMCS1_CH1_RX_SAR K_DMADDR_BASE_SMCS1 + 0x28 #define K_DMADD_SMCS1_CH1_RX_EAR K_DMADDR_BASE_SMCS1 + 0x2A #define K_DMADD_SMCS1_CH1_RX_CAR K_DMADDR_BASE_SMCS1 + 0x2C #define K_DMADD_SMCS1_CH1_STAR K_DMADDR_BASE_SMCS1 + 0x2F #define K_DMADD_SMCS1_CH2_DSM_MODR K_DMADDR_BASE_SMCS1 + 0x30 #define K_DMADD_SMCS1_CH2_DSM_CMDR K_DMADDR_BASE_SMCS1 + 0x31 #define K_DMADD_SMCS1_CH2_DSM_STAR K_DMADDR_BASE_SMCS1 + 0x32 #define K_DMADD_SMCS1_CH2_DSM_TSTR K_DMADDR_BASE_SMCS1 + 0x33 #define K_DMADD_SMCS1_CH2_ADDR K_DMADDR_BASE_SMCS1 + 0x34 #define K_DMADD_SMCS1_CH2_RT_ADDR K_DMADDR_BASE_SMCS1 + 0x35 #define K_DMADD_SMCS1_CH2_PR_STAR K_DMADDR_BASE_SMCS1 + 0x36 #define K_DMADD_SMCS1_CH2_CNTRL1 K_DMADDR_BASE_SMCS1 + 0x38 #define K_DMADD_SMCS1_CH2_CNTRL2 K_DMADDR_BASE_SMCS1 + 0x39 #define K_DMADD_SMCS1_CH2_HTID K_DMADDR_BASE_SMCS1 + 0x3A #define K_DMADD_SMCS1_CH2_HCNTRL K_DMADDR_BASE_SMCS1 + 0x3B #define K_DMADD_SMCS1_CH2_ESR1 K_DMADDR_BASE_SMCS1 + 0x3C #define K_DMADD_SMCS1_CH2_ESR2 K_DMADDR_BASE_SMCS1 + 0x3D #define K_DMADD_SMCS1_CH2_COMICFG K_DMADDR_BASE_SMCS1 + 0x3F #define K_DMADD_SMCS1_CH2_TX_SAR K_DMADDR_BASE_SMCS1 + 0x40 #define K_DMADD_SMCS1_CH2_TX_EAR K_DMADDR_BASE_SMCS1 + 0x42 #define K_DMADD_SMCS1_CH2_TX_CAR K_DMADDR_BASE_SMCS1 + 0x44 #define K_DMADD_SMCS1_CH2_TX_FIFO K_DMADDR_BASE_SMCS1 + 0x46 #define K_DMADD_SMCS1_CH2_TX_EOPB K_DMADDR_BASE_SMCS1 + 0x47 #define K_DMADD_SMCS1_CH2_RX_SAR K_DMADDR_BASE_SMCS1 + 0x48 #define K_DMADD_SMCS1_CH2_RX_EAR K_DMADDR_BASE_SMCS1 + 0x4A #define K_DMADD_SMCS1_CH2_RX_CAR K_DMADDR_BASE_SMCS1 + 0x4C #define K_DMADD_SMCS1_CH2_RX_FIFO K_DMADDR_BASE_SMCS1 + 0x4E #define K_DMADD_SMCS1_CH2_STAR K_DMADDR_BASE_SMCS1 + 0x4F #define K_DMADD_SMCS1_CH3_DSM_MODR K_DMADDR_BASE_SMCS1 + 0x50 #define K_DMADD_SMCS1_CH3_DSM_CMDR K_DMADDR_BASE_SMCS1 + 0x51 #define K_DMADD_SMCS1_CH3_DSM_STAR K_DMADDR_BASE_SMCS1 + 0x52 #define K_DMADD_SMCS1_CH3_DSM_TSTR K_DMADDR_BASE_SMCS1 + 0x53 #define K_DMADD_SMCS1_CH3_ADDR K_DMADDR_BASE_SMCS1 + 0x54 #define K_DMADD_SMCS1_CH3_RT_ADDR K_DMADDR_BASE_SMCS1 + 0x55 #define K_DMADD_SMCS1_CH3_PR_STAR K_DMADDR_BASE_SMCS1 + 0x56 #define K_DMADD_SMCS1_CH3_CNTRL1 K_DMADDR_BASE_SMCS1 + 0x58 #define K_DMADD_SMCS1_CH3_CNTRL2 K_DMADDR_BASE_SMCS1 + 0x59 #define K_DMADD_SMCS1_CH3_HTID K_DMADDR_BASE_SMCS1 + 0x5A #define K_DMADD_SMCS1_CH3_HCNTRL K_DMADDR_BASE_SMCS1 + 0x5B #define K_DMADD_SMCS1_CH3_ESR1 K_DMADDR_BASE_SMCS1 + 0x5C #define K_DMADD_SMCS1_CH3_ESR2 K_DMADDR_BASE_SMCS1 + 0x5D #define K_DMADD_SMCS1_CH3_COMICFG K_DMADDR_BASE_SMCS1 + 0x5F #define K_DMADD_SMCS1_CH3_TX_SAR K_DMADDR_BASE_SMCS1 + 0x60 #define K_DMADD_SMCS1_CH3_TX_EAR K_DMADDR_BASE_SMCS1 + 0x62 #define K_DMADD_SMCS1_CH3_TX_CAR K_DMADDR_BASE_SMCS1 + 0x64 #define K_DMADD_SMCS1_CH3_TX_FIFO K_DMADDR_BASE_SMCS1 + 0x66 #define K_DMADD_SMCS1_CH3_TX_EOPB K_DMADDR_BASE_SMCS1 + 0x67 #define K_DMADD_SMCS1_CH3_RX_SAR K_DMADDR_BASE_SMCS1 + 0x68 #define K_DMADD_SMCS1_CH3_RX_EAR K_DMADDR_BASE_SMCS1 + 0x6A #define K_DMADD_SMCS1_CH3_RX_CAR K_DMADDR_BASE_SMCS1 + 0x6C #define K_DMADD_SMCS1_CH3_RX_FIFO K_DMADDR_BASE_SMCS1 + 0x6E #define K_DMADD_SMCS1_CH3_STAR K_DMADDR_BASE_SMCS1 + 0x6F #define K_DMADD_SMCS2_SICR K_DMADDR_BASE_SMCS2 + 0x00 #define K_DMADD_SMCS2_TRS_CTRL K_DMADDR_BASE_SMCS2 + 0x01 #define K_DMADD_SMCS2_RT_CTRL K_DMADDR_BASE_SMCS2 + 0x02 #define K_DMADD_SMCS2_ISR K_DMADDR_BASE_SMCS2 + 0x04 #define K_DMADD_SMCS2_IMR K_DMADDR_BASE_SMCS2 + 0x08 #define K_DMADD_SMCS2_COMI_CS0R K_DMADDR_BASE_SMCS2 + 0x0C #define K_DMADD_SMCS2_COMI_ACR K_DMADDR_BASE_SMCS2 + 0x0E #define K_DMADD_SMCS2_PRCIR K_DMADDR_BASE_SMCS2 + 0x0F #define K_DMADD_SMCS2_CH4_DSM_MODR K_DMADDR_BASE_SMCS2 + 0x10 #define K_DMADD_SMCS2_CH4_DSM_CMDR K_DMADDR_BASE_SMCS2 + 0x11 #define K_DMADD_SMCS2_CH4_DSM_STAR K_DMADDR_BASE_SMCS2 + 0x12 #define K_DMADD_SMCS2_CH4_DSM_TSTR K_DMADDR_BASE_SMCS2 + 0x13 #define K_DMADD_SMCS2_CH4_ADDR K_DMADDR_BASE_SMCS2 + 0x14 #define K_DMADD_SMCS2_CH4_RT_ADDR K_DMADDR_BASE_SMCS2 + 0x15 #define K_DMADD_SMCS2_CH4_PR_STAR K_DMADDR_BASE_SMCS2 + 0x16 #define K_DMADD_SMCS2_CH4_CNTRL1 K_DMADDR_BASE_SMCS2 + 0x18 #define K_DMADD_SMCS2_CH4_CNTRL2 K_DMADDR_BASE_SMCS2 + 0x19 #define K_DMADD_SMCS2_CH4_HTID K_DMADDR_BASE_SMCS2 + 0x1A #define K_DMADD_SMCS2_CH4_HCNTRL K_DMADDR_BASE_SMCS2 + 0x1B #define K_DMADD_SMCS2_CH4_ESR1 K_DMADDR_BASE_SMCS2 + 0x1C #define K_DMADD_SMCS2_CH4_ESR2 K_DMADDR_BASE_SMCS2 + 0x1D #define K_DMADD_SMCS2_CH4_COMICFG K_DMADDR_BASE_SMCS2 + 0x1F #define K_DMADD_SMCS2_CH4_TX_SAR K_DMADDR_BASE_SMCS2 + 0x20 #define K_DMADD_SMCS2_CH4_TX_EAR K_DMADDR_BASE_SMCS2 + 0x22 #define K_DMADD_SMCS2_CH4_TX_CAR K_DMADDR_BASE_SMCS2 + 0x24 #define K_DMADD_SMCS2_CH4_TX_EOPB K_DMADDR_BASE_SMCS2 + 0x27 #define K_DMADD_SMCS2_CH4_RX_SAR K_DMADDR_BASE_SMCS2 + 0x28 #define K_DMADD_SMCS2_CH4_RX_EAR K_DMADDR_BASE_SMCS2 + 0x2A #define K_DMADD_SMCS2_CH4_RX_CAR K_DMADDR_BASE_SMCS2 + 0x2C #define K_DMADD_SMCS2_CH4_STAR K_DMADDR_BASE_SMCS2 + 0x2F #define K_DMADD_SMCS2_CH5_DSM_MODR K_DMADDR_BASE_SMCS2 + 0x30 #define K_DMADD_SMCS2_CH5_DSM_CMDR K_DMADDR_BASE_SMCS2 + 0x31 #define K_DMADD_SMCS2_CH5_DSM_STAR K_DMADDR_BASE_SMCS2 + 0x32 #define K_DMADD_SMCS2_CH5_DSM_TSTR K_DMADDR_BASE_SMCS2 + 0x33 #define K_DMADD_SMCS2_CH5_ADDR K_DMADDR_BASE_SMCS2 + 0x34 #define K_DMADD_SMCS2_CH5_RT_ADDR K_DMADDR_BASE_SMCS2 + 0x35 #define K_DMADD_SMCS2_CH5_PR_STAR K_DMADDR_BASE_SMCS2 + 0x36 #define K_DMADD_SMCS2_CH5_CNTRL1 K_DMADDR_BASE_SMCS2 + 0x38 #define K_DMADD_SMCS2_CH5_CNTRL2 K_DMADDR_BASE_SMCS2 + 0x39 #define K_DMADD_SMCS2_CH5_HTID K_DMADDR_BASE_SMCS2 + 0x3A #define K_DMADD_SMCS2_CH5_HCNTRL K_DMADDR_BASE_SMCS2 + 0x3B #define K_DMADD_SMCS2_CH5_ESR1 K_DMADDR_BASE_SMCS2 + 0x3C #define K_DMADD_SMCS2_CH5_ESR2 K_DMADDR_BASE_SMCS2 + 0x3D #define K_DMADD_SMCS2_CH5_COMICFG K_DMADDR_BASE_SMCS2 + 0x3F #define K_DMADD_SMCS2_CH5_TX_SAR K_DMADDR_BASE_SMCS2 + 0x40 #define K_DMADD_SMCS2_CH5_TX_EAR K_DMADDR_BASE_SMCS2 + 0x42 #define K_DMADD_SMCS2_CH5_TX_CAR K_DMADDR_BASE_SMCS2 + 0x44 #define K_DMADD_SMCS2_CH5_TX_FIFO K_DMADDR_BASE_SMCS2 + 0x46 #define K_DMADD_SMCS2_CH5_TX_EOPB K_DMADDR_BASE_SMCS2 + 0x47 #define K_DMADD_SMCS2_CH5_RX_SAR K_DMADDR_BASE_SMCS2 + 0x48 #define K_DMADD_SMCS2_CH5_RX_EAR K_DMADDR_BASE_SMCS2 + 0x4A #define K_DMADD_SMCS2_CH5_RX_CAR K_DMADDR_BASE_SMCS2 + 0x4C #define K_DMADD_SMCS2_CH5_RX_FIFO K_DMADDR_BASE_SMCS2 + 0x4E #define K_DMADD_SMCS2_CH5_STAR K_DMADDR_BASE_SMCS2 + 0x4F #define K_DMADD_SMCS2_CH6_DSM_MODR K_DMADDR_BASE_SMCS2 + 0x50 #define K_DMADD_SMCS2_CH6_DSM_CMDR K_DMADDR_BASE_SMCS2 + 0x51 #define K_DMADD_SMCS2_CH6_DSM_STAR K_DMADDR_BASE_SMCS2 + 0x52 #define K_DMADD_SMCS2_CH6_DSM_TSTR K_DMADDR_BASE_SMCS2 + 0x53 #define K_DMADD_SMCS2_CH6_ADDR K_DMADDR_BASE_SMCS2 + 0x54 #define K_DMADD_SMCS2_CH6_RT_ADDR K_DMADDR_BASE_SMCS2 + 0x55 #define K_DMADD_SMCS2_CH6_PR_STAR K_DMADDR_BASE_SMCS2 + 0x56 #define K_DMADD_SMCS2_CH6_CNTRL1 K_DMADDR_BASE_SMCS2 + 0x58 #define K_DMADD_SMCS2_CH6_CNTRL2 K_DMADDR_BASE_SMCS2 + 0x59 #define K_DMADD_SMCS2_CH6_HTID K_DMADDR_BASE_SMCS2 + 0x5A #define K_DMADD_SMCS2_CH6_HCNTRL K_DMADDR_BASE_SMCS2 + 0x5B #define K_DMADD_SMCS2_CH6_ESR1 K_DMADDR_BASE_SMCS2 + 0x5C #define K_DMADD_SMCS2_CH6_ESR2 K_DMADDR_BASE_SMCS2 + 0x5D #define K_DMADD_SMCS2_CH6_COMICFG K_DMADDR_BASE_SMCS2 + 0x5F #define K_DMADD_SMCS2_CH6_TX_SAR K_DMADDR_BASE_SMCS2 + 0x60 #define K_DMADD_SMCS2_CH6_TX_EAR K_DMADDR_BASE_SMCS2 + 0x62 #define K_DMADD_SMCS2_CH6_TX_CAR K_DMADDR_BASE_SMCS2 + 0x64 #define K_DMADD_SMCS2_CH6_TX_FIFO K_DMADDR_BASE_SMCS2 + 0x66 #define K_DMADD_SMCS2_CH6_TX_EOPB K_DMADDR_BASE_SMCS2 + 0x67 #define K_DMADD_SMCS2_CH6_RX_SAR K_DMADDR_BASE_SMCS2 + 0x68 #define K_DMADD_SMCS2_CH6_RX_EAR K_DMADDR_BASE_SMCS2 + 0x6A #define K_DMADD_SMCS2_CH6_RX_CAR K_DMADDR_BASE_SMCS2 + 0x6C #define K_DMADD_SMCS2_CH6_RX_FIFO K_DMADDR_BASE_SMCS2 + 0x6E #define K_DMADD_SMCS2_CH6_STAR K_DMADDR_BASE_SMCS2 + 0x6F /* Used to perform ISR workaround (dummy writing after reading ISR) */ #define K_DMADD_SMCS1_DUMMY K_DMADDR_BASE_SMCS1 + 0x7F #define K_DMADD_SMCS2_DUMMY K_DMADDR_BASE_SMCS2 + 0x7F /* Number of memory position between two similar registers of consecutive channels in the same SMCS chip */ #define K_OFFSET_BETWEEN_SMCSCHANNELS 0x20 /* Selected bit groups, used to mask and preserve these bits */ /* CHx_DSM_MODR register */ #define K_BMASK_CHx_DSM_MODR_TXSPEED 0x7 /* bits 2:0 */ /* CHx_COMICFG register */ #define K_BMASK_CHx_COMICFG_TXPORTWIDTH 0x3 /* bits 1:0 */ #define K_BMASK_CHx_COMICFG_RXPORTWIDTH 0x30 /* bits 5:4 */ /* Positions of selected group of bits (= number of bytes to right-shift in order to have the group starting at position 0). Used in shifting operations and in set/clear bit operations. */ /* CHx_COMICFG register */ #define K_BPOS_CHx_COMICFG_EOPID 2 #define K_BPOS_CHx_COMICFG_RXPORTWIDTH 4 /* CHx_CNTRL1 register */ #define K_BPOS_CHx_CNTRL1_CHECKSUMENA 4 /* CHx_DSM_CMDR register */ #define K_BPOS_CHx_DSM_CMDR_STOPLINK 0 #define K_BPOS_CHx_DSM_CMDR_STARTTXNODE 1 /* CHx_DSM_STAR register */ #define K_BPOS_CHx_DSM_STAR_TXLINKRUNNIN 0 #define K_BPOS_CHx_DSM_STAR_NULLRECEIVED 3 /* SMCS transmission/reception channels */ #define K_SMCSCHANNEL_1 1 #define K_SMCSCHANNEL_2 2 #define K_SMCSCHANNEL_3 3 #define K_SMCSCHANNEL_4 4 #define K_SMCSCHANNEL_5 5 #define K_SMCSCHANNEL_6 6 /***************************************************************************** PROVIDED TYPES *****************************************************************************/ /***************************************************************************** PROVIDED VARIABLES *****************************************************************************/ #ifndef INCLUDE_DEFINE_ONLY /***************************************************************************** DECLARATION OF PROVIDED FUNCTIONS *****************************************************************************/ T_SR DSMCS_ReadSMCSReg(T_UNSIGNED_32 Register, T_UNSIGNED_32 *RegisterValue); T_SR DSMCS_WriteSMCSReg(T_UNSIGNED_32 Register, T_UNSIGNED_32 RegisterValue); T_UNSIGNED_32 DSMCS_GetRegAddressForChannel(T_UNSIGNED_32 Channel, T_UNSIGNED_32 AddressChannel1); T_VOID DSMCS_WriteBitInSMCSReg(T_UNSIGNED_32 Register, T_UNSIGNED_32 BitPosition, T_UNSIGNED_32 BitValue); T_BOOLEAN DSMCS_CheckBitInSMCSReg(T_UNSIGNED_32 Register, T_UNSIGNED_32 BitPosition); #endif /*INCLUDE_DEFINE_ONLY*/ #endif /* M_SMCSGE_H */